From 4565917bb034479a29c04f0b44124e7f61585ccf Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 29 Aug 2023 16:14:29 -0400 Subject: pci: SLT must be RO current code sets PCI_SEC_LATENCY_TIMER to RW, but for pcie to pcie bridges it must be RO 0 according to pci express spec which says: This register does not apply to PCI Express. It must be read-only and hardwired to 00h. For PCI Express to PCI/PCI-X Bridges, refer to the [PCIe-to-PCI-PCI-X-Bridge] for requirements for this register. also, fix typo in comment where it's made writeable - this typo is likely what prevented us noticing we violate this requirement in the 1st place. Reported-by: Marcin Juszkiewicz Message-Id: Tested-by: Marcin Juszkiewicz Signed-off-by: Michael S. Tsirkin --- hw/core/machine.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'hw/core') diff --git a/hw/core/machine.c b/hw/core/machine.c index cb38b8cf4c..9ae8f793ae 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -32,6 +32,7 @@ #include "qemu/error-report.h" #include "sysemu/qtest.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" #include "hw/mem/nvdimm.h" #include "migration/global_state.h" #include "migration/vmstate.h" @@ -40,7 +41,9 @@ #include "hw/virtio/virtio-pci.h" #include "hw/virtio/virtio-net.h" -GlobalProperty hw_compat_8_1[] = {}; +GlobalProperty hw_compat_8_1[] = { + { TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" }, +}; const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1); GlobalProperty hw_compat_8_0[] = { -- cgit v1.2.3