From 70eb9f9cd1c0b519b31df8ab08ee2198b0e16176 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 3 Sep 2020 18:40:18 +0800 Subject: hw/riscv: Move riscv_htif model to hw/char This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move riscv_htif model to hw/char directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/char/meson.build | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/char/meson.build') diff --git a/hw/char/meson.build b/hw/char/meson.build index ae27932d00..3db623eeec 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -34,6 +34,7 @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c')) softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c')) +specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c')) specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c')) specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c')) -- cgit v1.2.3