From 3b08f0a92545ba06fbdeaae929a5172480300c33 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 8 Jul 2016 18:22:26 -0700 Subject: cputlb: Move probe_write out of softmmu_template.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- cputlb.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'cputlb.c') diff --git a/cputlb.c b/cputlb.c index 5575b733f5..0c9b77b0a0 100644 --- a/cputlb.c +++ b/cputlb.c @@ -527,6 +527,27 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ (ADDR) & TARGET_PAGE_MASK) +/* Probe for whether the specified guest write access is permitted. + * If it is not permitted then an exception will be taken in the same + * way as if this were a real write access (and we will not return). + * Otherwise the function will return, and there will be a valid + * entry in the TLB for this access. + */ +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, + uintptr_t retaddr) +{ + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; + + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + /* TLB entry is for a different page */ + if (!VICTIM_TLB_HIT(addr_write, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); + } + } +} + #define MMUSUFFIX _mmu #define DATA_SIZE 1 -- cgit v1.2.3