From 0d10df30384c22c5f683cbfebc42cee6cf83fed4 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 19 Feb 2021 14:45:44 +0000 Subject: hw/timer/sse-counter: Model the SSE Subsystem System Counter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SSE-300 includes a counter module; implement a model of it. This counter is documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-12-peter.maydell@linaro.org --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 26c9454823..68c37957cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -751,6 +751,8 @@ F: hw/misc/armsse-cpuid.c F: include/hw/misc/armsse-cpuid.h F: hw/misc/armsse-mhu.c F: include/hw/misc/armsse-mhu.h +F: hw/timer/sse-counter.c +F: include/hw/timer/sse-counter.h F: docs/system/arm/mps2.rst Musca -- cgit v1.2.3 From 0b8ceee822ae6d3bc4033c9b406c5f8d8c71ee6d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 19 Feb 2021 14:45:45 +0000 Subject: hw/timer/sse-timer: Model the SSE Subsystem System Timer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SSE-300 includes some timers which are a different kind to those in the SSE-200. Model them. These timers are documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-13-peter.maydell@linaro.org --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 68c37957cf..ea206fc900 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -753,6 +753,8 @@ F: hw/misc/armsse-mhu.c F: include/hw/misc/armsse-mhu.h F: hw/timer/sse-counter.c F: include/hw/timer/sse-counter.h +F: hw/timer/sse-timer.c +F: include/hw/timer/sse-timer.h F: docs/system/arm/mps2.rst Musca -- cgit v1.2.3 From 4239b311467bea86578d9da3cd22909de69d7af7 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 19 Feb 2021 14:45:53 +0000 Subject: hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU_PWRCTRL register block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SSE-300 has a new register block CPU_PWRCTRL. There is one instance of this per CPU in the system (so just one for the SSE-300), and as well as the usual CIDR/PIDR ID registers it has just one register, CPUPWRCFG. This register allows the guest to configure behaviour of the system in power-down and deep-sleep states. Since QEMU does not model those, we make the register a dummy reads-as-written implementation. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-21-peter.maydell@linaro.org --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index ea206fc900..bd863cfeca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -747,6 +747,8 @@ F: hw/misc/iotkit-sysctl.c F: include/hw/misc/iotkit-sysctl.h F: hw/misc/iotkit-sysinfo.c F: include/hw/misc/iotkit-sysinfo.h +F: hw/misc/armsse-cpu-pwrctrl.c +F: include/hw/misc/armsse-cpu-pwrctrl.h F: hw/misc/armsse-cpuid.c F: include/hw/misc/armsse-cpuid.h F: hw/misc/armsse-mhu.c -- cgit v1.2.3 From 1eca58aa1db79b077abf8c031c4d600998a5438d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 19 Feb 2021 14:46:17 +0000 Subject: tests/qtest/sse-timer-test: Add simple test of the SSE counter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a simple qtest to exercise the new system counter device in the SSE-300. We'll add tests of the system timer device here too, so this includes scaffolding (register definitions, etc) for those. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210219144617.4782-45-peter.maydell@linaro.org --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index bd863cfeca..be8385255d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -757,6 +757,7 @@ F: hw/timer/sse-counter.c F: include/hw/timer/sse-counter.h F: hw/timer/sse-timer.c F: include/hw/timer/sse-timer.h +F: tests/qtest/sse-timer-test.c F: docs/system/arm/mps2.rst Musca -- cgit v1.2.3