From e8a484603146f7e2523749ad06e6ea43b26cf411 Mon Sep 17 00:00:00 2001 From: Tom Musta Date: Mon, 21 Apr 2014 15:55:19 -0500 Subject: target-ppc: Introduce DFP Extract Biased Exponent Add emulation of the PowerPC Decimal Floating Point Extract Biased Exponent instructions dxex[q][.]. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/dfp_helper.c | 31 +++++++++++++++++++++++++++++++ target-ppc/helper.h | 2 ++ target-ppc/translate.c | 4 ++++ 3 files changed, 37 insertions(+) diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c index c6c104b739..8c8ee795c7 100644 --- a/target-ppc/dfp_helper.c +++ b/target-ppc/dfp_helper.c @@ -1121,3 +1121,34 @@ void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *b, uint32_t s) \ DFP_HELPER_ENBCD(denbcd, 64) DFP_HELPER_ENBCD(denbcdq, 128) + +#define DFP_HELPER_XEX(op, size) \ +void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *b) \ +{ \ + struct PPC_DFP dfp; \ + \ + dfp_prepare_decimal##size(&dfp, 0, b, env); \ + \ + if (unlikely(decNumberIsSpecial(&dfp.b))) { \ + if (decNumberIsInfinite(&dfp.b)) { \ + *t = -1; \ + } else if (decNumberIsSNaN(&dfp.b)) { \ + *t = -3; \ + } else if (decNumberIsQNaN(&dfp.b)) { \ + *t = -2; \ + } else { \ + assert(0); \ + } \ + } else { \ + if ((size) == 64) { \ + *t = dfp.b.exponent + 398; \ + } else if ((size) == 128) { \ + *t = dfp.b.exponent + 6176; \ + } else { \ + assert(0); \ + } \ + } \ +} + +DFP_HELPER_XEX(dxex, 64) +DFP_HELPER_XEX(dxexq, 128) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 1b40ce5e43..b99ca809a9 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -658,3 +658,5 @@ DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32) DEF_HELPER_4(ddedpdq, void, env, fprp, fprp, i32) DEF_HELPER_4(denbcd, void, env, fprp, fprp, i32) DEF_HELPER_4(denbcdq, void, env, fprp, fprp, i32) +DEF_HELPER_3(dxex, void, env, fprp, fprp) +DEF_HELPER_3(dxexq, void, env, fprp, fprp) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ea5df2f77f..4cc93dff48 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -8398,6 +8398,8 @@ GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP) GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP) GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP) GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP) +GEN_DFP_T_B_Rc(dxex) +GEN_DFP_T_B_Rc(dxexq) /*** SPE extension ***/ /* Register moves */ @@ -11367,6 +11369,8 @@ GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a), GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a), GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a), GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a), +GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b), +GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b), #undef GEN_SPE #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) -- cgit v1.2.3