From e79d27cb322b60b460b709d2c74ff7d77cde0565 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 16 Jul 2020 02:30:56 -0700 Subject: hw/riscv: sifive_e: Correct debug block size Currently the debug region size is set to 0x100, but according to FE310-G000 and FE310-G002 manuals: FE310-G000: 0x100 - 0xFFF FE310-G002: 0x0 - 0xFFF Change the size to 0x1000 that applies to both. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/riscv/sifive_e.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 7bb97b463d..c8b060486a 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -54,7 +54,7 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } sifive_e_memmap[] = { - [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, + [SIFIVE_E_DEBUG] = { 0x0, 0x1000 }, [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, -- cgit v1.2.3