From c6c99c3f175fa3f7e0d27c57c32b7029648a7407 Mon Sep 17 00:00:00 2001 From: aurel32 Date: Mon, 10 Mar 2008 00:12:14 +0000 Subject: GT64XXX: fix endianness issues: - Byte swapping for internal GT64XXX registers is controlled by the bit 12 of the Configuration Register and not by the PCI Internal Command register. - The bit 0 of the PCI Internal Command register controls byte swapping for PCI access *except for the internal PCI device*, that is when both bus and device numbers are 0. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4035 c046a42c-6fe2-441c-8c8c-71466251a162 --- hw/gt64xxx.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c index 46d6a762de..8e8adadd25 100644 --- a/hw/gt64xxx.c +++ b/hw/gt64xxx.c @@ -309,7 +309,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr, GT64120State *s = opaque; uint32_t saddr; - if (!(s->regs[GT_PCI0_CMD] & 1)) + if (!(s->regs[GT_CPU] & 0x00001000)) val = bswap32(val); saddr = (addr & 0xfff) >> 2; @@ -530,7 +530,10 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr, s->pci->config_reg = val & 0x80fffffc; break; case GT_PCI0_CFGDATA: - pci_host_data_writel(s->pci, 0, val); + if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci->config_reg & 0x00fff800)) + val = bswap32(val); + if (s->pci->config_reg & (1u << 31)) + pci_data_write(s->pci->bus, s->pci->config_reg, val, 4); break; /* Interrupts */ @@ -767,7 +770,12 @@ static uint32_t gt64120_readl (void *opaque, val = s->pci->config_reg; break; case GT_PCI0_CFGDATA: - val = pci_host_data_readl(s->pci, 0); + if (!(s->pci->config_reg & (1 << 31))) + val = 0xffffffff; + else + val = pci_data_read(s->pci->bus, s->pci->config_reg, 4); + if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci->config_reg & 0x00fff800)) + val = bswap32(val); break; case GT_PCI0_CMD: @@ -840,7 +848,7 @@ static uint32_t gt64120_readl (void *opaque, break; } - if (!(s->regs[GT_PCI0_CMD] & 1)) + if (!(s->regs[GT_CPU] & 0x00001000)) val = bswap32(val); return val; @@ -1069,7 +1077,6 @@ static void gt64120_reset(void *opaque) s->regs[GT_PCI1_CFGADDR] = 0x00000000; s->regs[GT_PCI1_CFGDATA] = 0x00000000; s->regs[GT_PCI0_CFGADDR] = 0x00000000; - s->regs[GT_PCI0_CFGDATA] = 0x00000000; /* Interrupt registers are all zeroed at reset */ @@ -1114,8 +1121,10 @@ PCIBus *pci_gt64120_init(qemu_irq *pic) (void)&pci_host_data_writeb; /* avoid warning */ (void)&pci_host_data_writew; /* avoid warning */ + (void)&pci_host_data_writel; /* avoid warning */ (void)&pci_host_data_readb; /* avoid warning */ (void)&pci_host_data_readw; /* avoid warning */ + (void)&pci_host_data_readl; /* avoid warning */ s = qemu_mallocz(sizeof(GT64120State)); s->pci = qemu_mallocz(sizeof(GT64120PCIState)); -- cgit v1.2.3