From 9ee6f678f473007e252934d6acd09c24490d9d42 Mon Sep 17 00:00:00 2001 From: Bharata B Rao Date: Fri, 10 Feb 2017 12:53:05 +0530 Subject: softfloat: Add round-to-odd rounding mode Power ISA 3.0 introduces a few quadruple precision floating point instructions that support round-to-odd rounding mode. The round-to-odd mode is explained as under: Let Z be the intermediate arithmetic result or the operand of a convert operation. If Z can be represented exactly in the target format, the result is Z. Otherwise the result is either Z1 or Z2 whichever is odd. Here Z1 and Z2 are the next larger and smaller numbers representable in the target format respectively. Signed-off-by: Bharata B Rao Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- fpu/softfloat.c | 21 ++++++++++++++++++++- include/fpu/softfloat.h | 2 ++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c295f3183f..5ccba76481 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -623,6 +623,9 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig, case float_round_down: roundIncrement = zSign ? 0x3ff : 0; break; + case float_round_to_odd: + roundIncrement = (zSig & 0x400) ? 0 : 0x3ff; + break; default: abort(); } @@ -632,8 +635,10 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig, || ( ( zExp == 0x7FD ) && ( (int64_t) ( zSig + roundIncrement ) < 0 ) ) ) { + bool overflow_to_inf = roundingMode != float_round_to_odd && + roundIncrement != 0; float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat64( zSign, 0x7FF, - ( roundIncrement == 0 )); + return packFloat64(zSign, 0x7FF, -(!overflow_to_inf)); } if ( zExp < 0 ) { if (status->flush_to_zero) { @@ -651,6 +656,13 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig, if (isTiny && roundBits) { float_raise(float_flag_underflow, status); } + if (roundingMode == float_round_to_odd) { + /* + * For round-to-odd case, the roundIncrement depends on + * zSig which just changed. + */ + roundIncrement = (zSig & 0x400) ? 0 : 0x3ff; + } } } if (roundBits) { @@ -1149,6 +1161,9 @@ static float128 roundAndPackFloat128(flag zSign, int32_t zExp, case float_round_down: increment = zSign && zSig2; break; + case float_round_to_odd: + increment = !(zSig1 & 0x1) && zSig2; + break; default: abort(); } @@ -1168,6 +1183,7 @@ static float128 roundAndPackFloat128(flag zSign, int32_t zExp, if ( ( roundingMode == float_round_to_zero ) || ( zSign && ( roundingMode == float_round_up ) ) || ( ! zSign && ( roundingMode == float_round_down ) ) + || (roundingMode == float_round_to_odd) ) { return packFloat128( @@ -1215,6 +1231,9 @@ static float128 roundAndPackFloat128(flag zSign, int32_t zExp, case float_round_down: increment = zSign && zSig2; break; + case float_round_to_odd: + increment = !(zSig1 & 0x1) && zSig2; + break; default: abort(); } diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 842ec6b22a..8a39028664 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -180,6 +180,8 @@ enum { float_round_up = 2, float_round_to_zero = 3, float_round_ties_away = 4, + /* Not an IEEE rounding mode: round to the closest odd mantissa value */ + float_round_to_odd = 5, }; /*---------------------------------------------------------------------------- -- cgit v1.2.3