From 66896cb803b4865c0c35b218dbc407e1fcf7f7f7 Mon Sep 17 00:00:00 2001 From: aurel32 Date: Fri, 13 Mar 2009 09:34:48 +0000 Subject: tcg: rename bswap_i32/i64 functions Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-arm/translate.c | 12 ++++++------ target-i386/translate.c | 6 +++--- target-m68k/translate.c | 2 +- target-ppc/translate.c | 22 +++++++++++----------- tcg/arm/tcg-target.h | 2 +- tcg/hppa/tcg-target.h | 2 +- tcg/i386/tcg-target.c | 4 ++-- tcg/i386/tcg-target.h | 2 +- tcg/sparc/tcg-target.h | 4 ++-- tcg/tcg-op.h | 18 +++++++++--------- tcg/tcg-opc.h | 8 ++++---- tcg/x86_64/tcg-target.c | 8 ++++---- tcg/x86_64/tcg-target.h | 4 ++-- 13 files changed, 47 insertions(+), 47 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 3cef021155..7c3d4724d4 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5162,7 +5162,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) NEON_GET_REG(T0, rm, pass * 2); NEON_GET_REG(T1, rm, pass * 2 + 1); switch (size) { - case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break; + case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break; case 1: gen_swap_half(cpu_T[0]); break; case 2: /* no-op */ break; default: abort(); @@ -5173,7 +5173,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) } else { gen_op_movl_T0_T1(); switch (size) { - case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break; + case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break; case 1: gen_swap_half(cpu_T[0]); break; default: abort(); } @@ -5315,7 +5315,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) switch (op) { case 1: /* VREV32 */ switch (size) { - case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break; + case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break; case 1: gen_swap_half(cpu_T[0]); break; default: return 1; } @@ -6568,7 +6568,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) if (insn & (1 << 7)) gen_rev16(tmp); else - tcg_gen_bswap_i32(tmp, tmp); + tcg_gen_bswap32_i32(tmp, tmp); } store_reg(s, rd, tmp); } else { @@ -7384,7 +7384,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) gen_helper_rbit(tmp, tmp); break; case 0x08: /* rev */ - tcg_gen_bswap_i32(tmp, tmp); + tcg_gen_bswap32_i32(tmp, tmp); break; case 0x09: /* rev16 */ gen_rev16(tmp); @@ -8518,7 +8518,7 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s) rd = insn & 0x7; tmp = load_reg(s, rn); switch ((insn >> 6) & 3) { - case 0: tcg_gen_bswap_i32(tmp, tmp); break; + case 0: tcg_gen_bswap32_i32(tmp, tmp); break; case 1: gen_rev16(tmp); break; case 3: gen_revsh(tmp); break; default: goto illegal_op; diff --git a/target-i386/translate.c b/target-i386/translate.c index 4b894fd708..6eb12ce1e3 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -6640,7 +6640,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) #ifdef TARGET_X86_64 if (dflag == 2) { gen_op_mov_TN_reg(OT_QUAD, 0, reg); - tcg_gen_bswap_i64(cpu_T[0], cpu_T[0]); + tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); gen_op_mov_reg_T0(OT_QUAD, reg); } else { @@ -6649,14 +6649,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) tmp0 = tcg_temp_new_i32(); tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]); - tcg_gen_bswap_i32(tmp0, tmp0); + tcg_gen_bswap32_i32(tmp0, tmp0); tcg_gen_extu_i32_i64(cpu_T[0], tmp0); gen_op_mov_reg_T0(OT_LONG, reg); } #else { gen_op_mov_TN_reg(OT_LONG, 0, reg); - tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); + tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); gen_op_mov_reg_T0(OT_LONG, reg); } #endif diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 7a0d85d338..4e3cf4aa2e 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1247,7 +1247,7 @@ DISAS_INSN(byterev) TCGv reg; reg = DREG(insn, 0); - tcg_gen_bswap_i32(reg, reg); + tcg_gen_bswap32_i32(reg, reg); } DISAS_INSN(move) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 0368c37430..d30bd35395 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2621,11 +2621,11 @@ static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2 #if defined(TARGET_PPC64) TCGv_i32 t0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, arg1); - tcg_gen_bswap_i32(t0, t0); + tcg_gen_bswap32_i32(t0, t0); tcg_gen_extu_i32_tl(arg1, t0); tcg_temp_free_i32(t0); #else - tcg_gen_bswap_i32(arg1, arg1); + tcg_gen_bswap32_i32(arg1, arg1); #endif } } @@ -2638,7 +2638,7 @@ static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); t0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, arg1); - tcg_gen_bswap_i32(t0, t0); + tcg_gen_bswap32_i32(t0, t0); tcg_gen_ext_i32_tl(arg1, t0); tcg_temp_free_i32(t0); } else @@ -2650,7 +2650,7 @@ static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv a { tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); if (unlikely(ctx->le_mode)) { - tcg_gen_bswap_i64(arg1, arg1); + tcg_gen_bswap64_i64(arg1, arg1); } } @@ -2694,7 +2694,7 @@ static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) TCGv t1; t0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, arg1); - tcg_gen_bswap_i32(t0, t0); + tcg_gen_bswap32_i32(t0, t0); t1 = tcg_temp_new(); tcg_gen_extu_i32_tl(t1, t0); tcg_temp_free_i32(t0); @@ -2702,7 +2702,7 @@ static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) tcg_temp_free(t1); #else TCGv t0 = tcg_temp_new_i32(); - tcg_gen_bswap_i32(t0, arg1); + tcg_gen_bswap32_i32(t0, arg1); tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); tcg_temp_free(t0); #endif @@ -2715,7 +2715,7 @@ static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv a { if (unlikely(ctx->le_mode)) { TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_bswap_i64(t0, arg1); + tcg_gen_bswap64_i64(t0, arg1); tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); tcg_temp_free_i64(t0); } else @@ -3014,11 +3014,11 @@ static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg #if defined(TARGET_PPC64) TCGv_i32 t0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, arg1); - tcg_gen_bswap_i32(t0, t0); + tcg_gen_bswap32_i32(t0, t0); tcg_gen_extu_i32_tl(arg1, t0); tcg_temp_free_i32(t0); #else - tcg_gen_bswap_i32(arg1, arg1); + tcg_gen_bswap32_i32(arg1, arg1); #endif } } @@ -3062,7 +3062,7 @@ static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2 TCGv t1; t0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, arg1); - tcg_gen_bswap_i32(t0, t0); + tcg_gen_bswap32_i32(t0, t0); t1 = tcg_temp_new(); tcg_gen_extu_i32_tl(t1, t0); tcg_temp_free_i32(t0); @@ -3070,7 +3070,7 @@ static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2 tcg_temp_free(t1); #else TCGv t0 = tcg_temp_new_i32(); - tcg_gen_bswap_i32(t0, arg1); + tcg_gen_bswap32_i32(t0, arg1); tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); tcg_temp_free(t0); #endif diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index cccb8f9dbb..8f5016fc46 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -28,7 +28,7 @@ #undef TCG_TARGET_WORDS_BIGENDIAN #undef TCG_TARGET_HAS_div_i32 #undef TCG_TARGET_HAS_div_i64 -#undef TCG_TARGET_HAS_bswap_i32 +#undef TCG_TARGET_HAS_bswap32_i32 #define TCG_TARGET_HAS_ext8s_i32 #define TCG_TARGET_HAS_ext16s_i32 #define TCG_TARGET_HAS_neg_i32 diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h index 02dd294278..7ab6f0cede 100644 --- a/tcg/hppa/tcg-target.h +++ b/tcg/hppa/tcg-target.h @@ -78,7 +78,7 @@ enum { //#define TCG_TARGET_HAS_ext8s_i32 //#define TCG_TARGET_HAS_ext16s_i32 //#define TCG_TARGET_HAS_bswap16_i32 -//#define TCG_TARGET_HAS_bswap_i32 +//#define TCG_TARGET_HAS_bswap32_i32 /* Note: must be synced with dyngen-exec.h */ #define TCG_AREG0 TCG_REG_R17 diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index c8f7fff7e5..d8b5563bd3 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -1034,7 +1034,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, tcg_out_brcond2(s, args, const_args); break; - case INDEX_op_bswap_i32: + case INDEX_op_bswap32_i32: tcg_out_opc(s, (0xc8 + args[0]) | P_EXT); break; @@ -1130,7 +1130,7 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } }, { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } }, - { INDEX_op_bswap_i32, { "r", "0" } }, + { INDEX_op_bswap32_i32, { "r", "0" } }, { INDEX_op_neg_i32, { "r", "0" } }, diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b5dec57dcf..60450a4462 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -45,7 +45,7 @@ enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 /* optional instructions */ -#define TCG_TARGET_HAS_bswap_i32 +#define TCG_TARGET_HAS_bswap32_i32 #define TCG_TARGET_HAS_neg_i32 #define TCG_TARGET_HAS_not_i32 #define TCG_TARGET_HAS_ext8s_i32 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 22bd9fed37..43ec8180f3 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -86,8 +86,8 @@ enum { #endif /* optional instructions */ -//#define TCG_TARGET_HAS_bswap_i32 -//#define TCG_TARGET_HAS_bswap_i64 +//#define TCG_TARGET_HAS_bswap32_i32 +//#define TCG_TARGET_HAS_bswap64_i64 //#define TCG_TARGET_HAS_neg_i32 //#define TCG_TARGET_HAS_neg_i64 diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 190a365b80..fa0f01cdd3 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1220,10 +1220,10 @@ static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) #endif } -static inline void tcg_gen_bswap_i32(TCGv_i32 ret, TCGv_i32 arg) +static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) { -#ifdef TCG_TARGET_HAS_bswap_i32 - tcg_gen_op2_i32(INDEX_op_bswap_i32, ret, arg); +#ifdef TCG_TARGET_HAS_bswap32_i32 + tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); #else TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); @@ -1300,14 +1300,14 @@ static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } -static inline void tcg_gen_bswap_i64(TCGv_i64 ret, TCGv_i64 arg) +static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) { TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_bswap_i32(t0, TCGV_LOW(arg)); - tcg_gen_bswap_i32(t1, TCGV_HIGH(arg)); + tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); + tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); tcg_gen_mov_i32(TCGV_LOW(ret), t1); tcg_gen_mov_i32(TCGV_HIGH(ret), t0); tcg_temp_free_i32(t0); @@ -1381,10 +1381,10 @@ static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); } -static inline void tcg_gen_bswap_i64(TCGv_i64 ret, TCGv_i64 arg) +static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) { -#ifdef TCG_TARGET_HAS_bswap_i64 - tcg_gen_op2_i64(INDEX_op_bswap_i64, ret, arg); +#ifdef TCG_TARGET_HAS_bswap64_i64 + tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); #else TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 560c8a7ada..c7f2b80d85 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -89,8 +89,8 @@ DEF2(ext8s_i32, 1, 1, 0, 0) #ifdef TCG_TARGET_HAS_ext16s_i32 DEF2(ext16s_i32, 1, 1, 0, 0) #endif -#ifdef TCG_TARGET_HAS_bswap_i32 -DEF2(bswap_i32, 1, 1, 0, 0) +#ifdef TCG_TARGET_HAS_bswap32_i32 +DEF2(bswap32_i32, 1, 1, 0, 0) #endif #ifdef TCG_TARGET_HAS_not_i32 DEF2(not_i32, 1, 1, 0, 0) @@ -149,8 +149,8 @@ DEF2(ext16s_i64, 1, 1, 0, 0) #ifdef TCG_TARGET_HAS_ext32s_i64 DEF2(ext32s_i64, 1, 1, 0, 0) #endif -#ifdef TCG_TARGET_HAS_bswap_i64 -DEF2(bswap_i64, 1, 1, 0, 0) +#ifdef TCG_TARGET_HAS_bswap64_i64 +DEF2(bswap64_i64, 1, 1, 0, 0) #endif #ifdef TCG_TARGET_HAS_not_i64 DEF2(not_i64, 1, 1, 0, 0) diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c index a840ac691d..b7c4aa613c 100644 --- a/tcg/x86_64/tcg-target.c +++ b/tcg/x86_64/tcg-target.c @@ -1094,10 +1094,10 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, args[3], P_REXW); break; - case INDEX_op_bswap_i32: + case INDEX_op_bswap32_i32: tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0); break; - case INDEX_op_bswap_i64: + case INDEX_op_bswap64_i64: tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0); break; @@ -1287,8 +1287,8 @@ static const TCGTargetOpDef x86_64_op_defs[] = { { INDEX_op_brcond_i64, { "r", "re" } }, - { INDEX_op_bswap_i32, { "r", "0" } }, - { INDEX_op_bswap_i64, { "r", "0" } }, + { INDEX_op_bswap32_i32, { "r", "0" } }, + { INDEX_op_bswap64_i64, { "r", "0" } }, { INDEX_op_neg_i32, { "r", "0" } }, { INDEX_op_neg_i64, { "r", "0" } }, diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h index b7e7decf68..79d22ab837 100644 --- a/tcg/x86_64/tcg-target.h +++ b/tcg/x86_64/tcg-target.h @@ -56,8 +56,8 @@ enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 /* optional instructions */ -#define TCG_TARGET_HAS_bswap_i32 -#define TCG_TARGET_HAS_bswap_i64 +#define TCG_TARGET_HAS_bswap32_i32 +#define TCG_TARGET_HAS_bswap64_i64 #define TCG_TARGET_HAS_neg_i32 #define TCG_TARGET_HAS_neg_i64 #define TCG_TARGET_HAS_not_i32 -- cgit v1.2.3