From 51f9b84e759c692575542627dd8d39ae216ac521 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sun, 2 Jan 2011 19:44:49 +0100 Subject: m48t59: Fix a wrong opaque passed to nvram read and write routines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes boot on PPC prep. Signed-off-by: Hervé Poussineau Signed-off-by: Aurelien Jarno --- hw/m48t59.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/m48t59.c b/hw/m48t59.c index 6991e2e8e1..2020487bbe 100644 --- a/hw/m48t59.c +++ b/hw/m48t59.c @@ -642,6 +642,7 @@ M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base, DeviceState *dev; SysBusDevice *s; M48t59SysBusState *d; + M48t59State *state; dev = qdev_create(NULL, "m48t59"); qdev_prop_set_uint32(dev, "type", type); @@ -649,18 +650,18 @@ M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base, qdev_prop_set_uint32(dev, "io_base", io_base); qdev_init_nofail(dev); s = sysbus_from_qdev(dev); + d = FROM_SYSBUS(M48t59SysBusState, s); + state = &d->state; sysbus_connect_irq(s, 0, IRQ); if (io_base != 0) { - register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); - register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); + register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state); + register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state); } if (mem_base != 0) { sysbus_mmio_map(s, 0, mem_base); } - d = FROM_SYSBUS(M48t59SysBusState, s); - - return &d->state; + return state; } M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type) -- cgit v1.2.3