From 5025388b5083f199b05cc252c2b031d9fc230391 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Thu, 28 Feb 2013 18:23:16 +0000 Subject: cadence_gem: Don't reset rx desc pointer on rx_en This doesn't happen in the real hardware. The Zynq TRM explicitly states that this bit has no effect on the rx descriptor pointer ("The receive queue pointer register is unaffected"). Signed-off-by: Peter Crosthwaite Message-id: 06fdf92b78ee62d8965779bafd29c8df1a5d2718.1360901435.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/cadence_gem.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c index a1ac069a20..61f1801273 100644 --- a/hw/cadence_gem.c +++ b/hw/cadence_gem.c @@ -1083,10 +1083,6 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, /* Reset to start of Q when transmit disabled. */ s->tx_desc_addr = s->regs[GEM_TXQBASE]; } - if (!(val & GEM_NWCTRL_RXENA)) { - /* Reset to start of Q when receive disabled. */ - s->rx_desc_addr = s->regs[GEM_RXQBASE]; - } if (val & GEM_NWCTRL_RXENA) { qemu_flush_queued_packets(qemu_get_queue(s->nic)); } -- cgit v1.2.3