From ed5abf46b3c414ef58e647145f19b3966700b206 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 20 Jan 2020 21:36:57 -0800 Subject: target/riscv: Correctly implement TSR trap As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level. This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set and we are in S-Mode. Signed-off-by: Alistair Francis Reviewed-by: Jonathan Behrens --- target/riscv/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 8736f689c2..c6412f680c 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -85,7 +85,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) } if (env->priv_ver >= PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TSR)) { + get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } -- cgit v1.2.3 From bfd05e8127353339e905a45990f3af379a2c2aec Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 24 Feb 2020 05:39:41 -0800 Subject: roms: opensbi: Upgrade from v0.5 to v0.6 Upgrade OpenSBI from v0.5 to v0.6 and the pre-built bios images. The v0.6 release includes the following commits: dd8ef28 firmware: Fix compile error for FW_PAYLOAD with latest GCC binutils 98f4a20 firmware: Introduce relocation lottery f728a0b include: Sync-up encoding with priv v1.12-draft and hypervisor v0.5-draft 18897aa include: Use _UL() and _ULL() for defines in riscv_encoding.h 7a13beb firmware: Add preferred boot HART field in struct fw_dynamic_info 215421c lib: Remove date and time from init message 838657c include: Remove ilen member of struct unpriv_trap b1d8c98 lib: No need to set VSSTATUS.MXR bit in get_insn() 0e1322b lib: Better naming of unpriv APIs for wider use 75f903d lib: Simplify trap parameters in sbi_ecall functions c96cc03 lib: Fix CPU capabilities detection function ab14f94 lib: Fix probe extension 813f7f4 lib: Add error detection for misa_extension dc40042 include: sbi_platform: fix compilation for GCC-9 bd732ae include: Add guest external interrupt related defines 6590a7d lib: Delegate guest page faults to HS-mode 4370f18 include: Extend struct sbi_trap_info for mtval2 and mtinst 086dbdf lib: Fix sbi_get_insn() for load guest page fault 2be424b lib: Extend trap redirection for hypervisor v0.5 spec 7219477 lib: Use MTINST CSR in misaligned load/store emulation b8732fe lib: Add replacement extension and function ids aa0ed1d lib: Remove redundant IPI types 1092663 lib: Add TIME extension in SBI 9777aee lib: Add IPI extension in SBI 9407202 lib: Add hfence instruction encoding 331ff6a lib: Support stage1 and stage2 tlb flushing 86a31f5 lib: Implement RFENCE extension c7d1b12 firmware: Return real DTB address when FW_xyz_FDT_ADDR is not defined 9beb573 firmware: Improve comments for fw_prev_arg1() and fw_next_arg1() fc6bd90 docs: Improve docs for FDT address passing 46a90d9 lib: utils: Support CLINT with 32bit MMIO access on RV64 system c0849cd platform: Add T-head C910 initial support e746673 lib: Remove unnecessary checks from init_coldboot() and init_warmboot() c3e406f lib: Add initial sbi_exit() API 55e191e lib: Add system early_exit and final_exit APIs 6469ed1 lib: Add timer exit API b325f6b lib: Add ipi exit API 1993182 lib: Add irqchip exit API 2aa43a1 lib: save/restore MIE CSR in sbi_hart_wait_for_coldboot() b0c9787 lib: do sbi_exit() upon halt IPI 15ed1e7 lib: improve system reboot and shutdown implementation 73c19e6 lib: zero-out memory allocated using sbi_scratch_alloc_offset() a67fd68 lib: Add sbi_init_count() API 049ad0b build: Use -ffreestanding e340bbf include: Add OPENSBI_EXTERNAL_SBI_TYPES in sbi_types.h b28b8ac docs: Add description of using OPENSBI_EXTERNAL_SBI_TYPES adf8b73 platform: thead/c910: Remove SBI_PLATFORM_HAS_PMP f95dd39 docs: platform: Update SiFive FU540 doc as-per U-Boot v2020.01 6ffe1be firmware: Fix placement of .align directives 7daccae platform: thead/c910: Don't enable L2 cache in warm boot a73d45c platform: thead/c910: Don't set plic/clint address in warm boot 30cdf00 scripts: Add C910 to platform list in the binary archive script 0492c5d include: Typo fix in comment for SBI_SCRATCH_SIZE define 046cc16 lib: Move struct sbi_ipi_data definition to sbi_ipi.c 3d2aaac lib: Introduce sbi_ipi_send_smode() API da9b76b lib: Introduce sbi_ipi_send_halt() API a8b4b83 lib: Introduce sbi_tlb_fifo_request() API 5f762d1 lib: Introduce sbi_ipi_event_create/destroy() APIs 817d50d lib: Drop _fifo from the name of various sbi_tlb_fifo_xyz() functions 84cd4fc lib: Initialize TLB management directly from coldboot/warmboot path 0a411bf include: Add generic and simple list handling APIs 37923c4 lib: Add dynamic registration of SBI extensions 7668502 lib: Factor-out SBI legacy extension 161b348 lib: Factor-out SBI replacement extensions 43ac621 lib: Factor-out SBI vendor extension 021b9e7 lib: Factor-out SBI base extension 85647a1 platform: template: typo fix in system reboot/shutdown names ac1c229 platform: Update UART base addresses for qemu/sifve_u d79173b platform: Add an platform ops to return platform specific tlb flush limit 2c2bbe7 platform: sifive/fu540: Set tlb range flush limit to zero 5ff1ab0 makefile: add support for building on macOS 6d0b4c5 platform: Drop qemu/sifive_u support 9a717ec platform: sifive: fu540: Add platform specific 'make run' cmd d6fa7f9 doc: sifive: fu540: Update QEMU instruction when using U-Boot as the payload 179edde lib: sbi_scratch: use bitwise ops in sbi_scratch_alloc_offset() 897b8fb lib: Use __builtin_ctzl() in pmp_get() 1a8ca08 lib: Initialize out value in SBI calls c2bfa2b lib: irqchip/plic: Disable all contexts and IRQs c2f23cc platform: Add Spike initial support a062200 platform: Remove stale options from config.mk files c03c8a1 scripts: Add Spike to platform list of binary archive script 29bb2a6 docs: platform: Add documentation for Spike platform 48b06ad ThirdPartyNotices: Fix doc styles 892e879 doc: coreboot: Fix doc styles fdfb533 doc: payload_linux: Fix doc styles 44d1296 doc: andes-ae350: Fix doc styles a8ef0b5 doc: ariane-fpga: Fix doc styles 82fd42f doc: qemu_virt: Fix doc styles f8ce996 doc: sifive_fu540: Fix doc styles 27a5c7f doc: thead-c910: Fix doc styles 0b41453 Revert "lib: Use __builtin_ctzl() in pmp_get()" c66543d lib: utils: htif: Fix 32-bit build bc874e3 lib: Don't check MIDELEG and MEDELEG at end of delegate_traps() 24c3082 lib: Print interrupt and exception delegation in boot prints 66fb729 platform: sifive: fu540: Add 32-bit specific fdt/payload addresses 3e7d666 platform: qemu: virt: Correct the typo in config.mk c3b3b8f lib: Fix typo in atomic exchange functions 3936243 lib: Use available hart mask for correct hbase value f8b3bb8 lib: Simplify the for-loop in sbi_ipi_send_many() ac5e821 include: Bump-up version to 0.6 Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 40984 -> 41280 bytes pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 49160 -> 53760 bytes pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin 45064 -> 49664 bytes roms/opensbi | 2 +- 4 files changed, 1 insertion(+), 1 deletion(-) diff --git a/pc-bios/opensbi-riscv32-virt-fw_jump.bin b/pc-bios/opensbi-riscv32-virt-fw_jump.bin index 6c5b7b89f6..c9654e7047 100644 Binary files a/pc-bios/opensbi-riscv32-virt-fw_jump.bin and b/pc-bios/opensbi-riscv32-virt-fw_jump.bin differ diff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin index 971f2be405..77f4dc8f83 100644 Binary files a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin and b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin differ diff --git a/pc-bios/opensbi-riscv64-virt-fw_jump.bin b/pc-bios/opensbi-riscv64-virt-fw_jump.bin index 45a5aed1ce..31e74d12ea 100644 Binary files a/pc-bios/opensbi-riscv64-virt-fw_jump.bin and b/pc-bios/opensbi-riscv64-virt-fw_jump.bin differ diff --git a/roms/opensbi b/roms/opensbi index be92da280d..ac5e821d50 160000 --- a/roms/opensbi +++ b/roms/opensbi @@ -1 +1 @@ -Subproject commit be92da280d87c38a2e0adc5d3f43bab7b5468f09 +Subproject commit ac5e821d50be631f26274765a59bc1b444ffd862 -- cgit v1.2.3 From a6fcc80bea1f062ffad330a1dcbc1e3d463a4493 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 24 Feb 2020 05:39:42 -0800 Subject: roms: opensbi: Add 32-bit firmware image for sifive_u machine Although the real world SiFive HiFive Unleashed board is a 64-bit hardware configuration, with QEMU it is possible to test 32-bit configuration with the same hardware features. This updates the roms Makefile to add the build rules for creating the 32-bit OpenSBI firmware image for sifive_u machine. A pre-built OpenSBI v0.6 image has been added as the default bios for 32-bit sifive_u machine. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- Makefile | 2 +- pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin | Bin 0 -> 49472 bytes roms/Makefile | 7 +++++++ 3 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin diff --git a/Makefile b/Makefile index 7df22fcc5d..ea0e08fc57 100644 --- a/Makefile +++ b/Makefile @@ -848,7 +848,7 @@ u-boot.e500 u-boot-sam460-20100605.bin \ qemu_vga.ndrv \ edk2-licenses.txt \ hppa-firmware.img \ -opensbi-riscv32-virt-fw_jump.bin \ +opensbi-riscv32-sifive_u-fw_jump.bin opensbi-riscv32-virt-fw_jump.bin \ opensbi-riscv64-sifive_u-fw_jump.bin opensbi-riscv64-virt-fw_jump.bin diff --git a/pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin b/pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin new file mode 100644 index 0000000000..bab13f597a Binary files /dev/null and b/pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin differ diff --git a/roms/Makefile b/roms/Makefile index 28e1e557b0..f9acf39954 100644 --- a/roms/Makefile +++ b/roms/Makefile @@ -66,6 +66,7 @@ default help: @echo " efi -- update UEFI (edk2) platform firmware" @echo " opensbi32-virt -- update OpenSBI for 32-bit virt machine" @echo " opensbi64-virt -- update OpenSBI for 64-bit virt machine" + @echo " opensbi32-sifive_u -- update OpenSBI for 32-bit sifive_u machine" @echo " opensbi64-sifive_u -- update OpenSBI for 64-bit sifive_u machine" @echo " bios-microvm -- update bios-microvm.bin (qboot)" @echo " clean -- delete the files generated by the previous" \ @@ -181,6 +182,12 @@ opensbi64-virt: PLATFORM="qemu/virt" cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-virt-fw_jump.bin +opensbi32-sifive_u: + $(MAKE) -C opensbi \ + CROSS_COMPILE=$(riscv32_cross_prefix) \ + PLATFORM="sifive/fu540" + cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin ../pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin + opensbi64-sifive_u: $(MAKE) -C opensbi \ CROSS_COMPILE=$(riscv64_cross_prefix) \ -- cgit v1.2.3 From b78c3296314b5bbb5f837e9b1dee7b8dde25573b Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 24 Feb 2020 05:39:43 -0800 Subject: riscv: sifive_u: Update BIOS_FILENAME for 32-bit Update BIOS_FILENAME to consider 32-bit bios image file name. Tested booting Linux v5.5 32-bit image (built from rv32_defconfig plus CONFIG_SOC_SIFIVE) with the default 32-bit bios image. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 156a003642..4409ea1ccc 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -56,7 +56,11 @@ #include -#define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" +#if defined(TARGET_RISCV32) +# define BIOS_FILENAME "opensbi-riscv32-sifive_u-fw_jump.bin" +#else +# define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" +#endif static const struct MemmapEntry { hwaddr base; -- cgit v1.2.3 From c6fc0fc1a71a0cb09b472cf36dded3c52bd77880 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 24 Feb 2020 05:39:44 -0800 Subject: gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add two GitLab jobs to build the OpenSBI firmware binaries. The first job builds a Docker image with the packages requisite to build OpenSBI, and stores this image in the GitLab registry. The second job pulls the image from the registry and builds the OpenSBI firmware binaries. The docker image is only rebuilt if the GitLab YAML or the Dockerfile is updated. The second job is only built when the roms/opensbi/ submodule is updated, when a git-ref starts with 'opensbi' or when the last commit contains 'OpenSBI'. The files generated are archived in the artifacts.zip file. With OpenSBI v0.6, it took 2 minutes 56 seconds to build the docker image, and 1 minute 24 seconds to generate the artifacts.zip with the firmware binaries (filesize: 111KiB). See: https://gitlab.com/lbmeng/qemu/pipelines/120520138 Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Bin Meng Signed-off-by: Palmer Dabbelt --- .gitlab-ci-opensbi.yml | 63 +++++++++++++++++++++++++++++++++++++++++ .gitlab-ci.d/opensbi/Dockerfile | 33 +++++++++++++++++++++ .gitlab-ci.yml | 1 + 3 files changed, 97 insertions(+) create mode 100644 .gitlab-ci-opensbi.yml create mode 100644 .gitlab-ci.d/opensbi/Dockerfile diff --git a/.gitlab-ci-opensbi.yml b/.gitlab-ci-opensbi.yml new file mode 100644 index 0000000000..dd051c0124 --- /dev/null +++ b/.gitlab-ci-opensbi.yml @@ -0,0 +1,63 @@ +docker-opensbi: + stage: build + rules: # Only run this job when the Dockerfile is modified + - changes: + - .gitlab-ci-opensbi.yml + - .gitlab-ci.d/opensbi/Dockerfile + when: always + image: docker:19.03.1 + services: + - docker:19.03.1-dind + variables: + GIT_DEPTH: 3 + IMAGE_TAG: $CI_REGISTRY_IMAGE:opensbi-cross-build + # We don't use TLS + DOCKER_HOST: tcp://docker:2375 + DOCKER_TLS_CERTDIR: "" + before_script: + - docker login -u $CI_REGISTRY_USER -p $CI_REGISTRY_PASSWORD $CI_REGISTRY + script: + - docker pull $IMAGE_TAG || true + - docker build --cache-from $IMAGE_TAG --tag $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA + --tag $IMAGE_TAG .gitlab-ci.d/opensbi + - docker push $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA + - docker push $IMAGE_TAG + +build-opensbi: + rules: # Only run this job when ... + - changes: # ... roms/opensbi/ is modified (submodule updated) + - roms/opensbi/* + when: always + - if: '$CI_COMMIT_REF_NAME =~ /^opensbi/' # or the branch/tag starts with 'opensbi' + when: always + - if: '$CI_COMMIT_MESSAGE =~ /opensbi/i' # or last commit description contains 'OpenSBI' + when: always + artifacts: + paths: # 'artifacts.zip' will contains the following files: + - pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin + - pc-bios/opensbi-riscv32-virt-fw_jump.bin + - pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin + - pc-bios/opensbi-riscv64-virt-fw_jump.bin + - opensbi32-virt-stdout.log + - opensbi32-virt-stderr.log + - opensbi64-virt-stdout.log + - opensbi64-virt-stderr.log + - opensbi32-sifive_u-stdout.log + - opensbi32-sifive_u-stderr.log + - opensbi64-sifive_u-stdout.log + - opensbi64-sifive_u-stderr.log + image: $CI_REGISTRY_IMAGE:opensbi-cross-build + variables: + GIT_DEPTH: 3 + script: # Clone the required submodules and build OpenSBI + - git submodule update --init roms/opensbi + - export JOBS=$(($(getconf _NPROCESSORS_ONLN) + 1)) + - echo "=== Using ${JOBS} simultaneous jobs ===" + - make -j${JOBS} -C roms/opensbi clean + - make -j${JOBS} -C roms opensbi32-virt 2>&1 1>opensbi32-virt-stdout.log | tee -a opensbi32-virt-stderr.log >&2 + - make -j${JOBS} -C roms/opensbi clean + - make -j${JOBS} -C roms opensbi64-virt 2>&1 1>opensbi64-virt-stdout.log | tee -a opensbi64-virt-stderr.log >&2 + - make -j${JOBS} -C roms/opensbi clean + - make -j${JOBS} -C roms opensbi32-sifive_u 2>&1 1>opensbi32-sifive_u-stdout.log | tee -a opensbi32-sifive_u-stderr.log >&2 + - make -j${JOBS} -C roms/opensbi clean + - make -j${JOBS} -C roms opensbi64-sifive_u 2>&1 1>opensbi64-sifive_u-stdout.log | tee -a opensbi64-sifive_u-stderr.log >&2 diff --git a/.gitlab-ci.d/opensbi/Dockerfile b/.gitlab-ci.d/opensbi/Dockerfile new file mode 100644 index 0000000000..4ba8a4de86 --- /dev/null +++ b/.gitlab-ci.d/opensbi/Dockerfile @@ -0,0 +1,33 @@ +# +# Docker image to cross-compile OpenSBI firmware binaries +# +FROM ubuntu:18.04 + +MAINTAINER Bin Meng + +# Install packages required to build OpenSBI +RUN apt update \ + && \ + \ + DEBIAN_FRONTEND=noninteractive \ + apt install --assume-yes --no-install-recommends \ + build-essential \ + ca-certificates \ + git \ + make \ + wget \ + && \ + \ + rm -rf /var/lib/apt/lists/* + +# Manually install the kernel.org "Crosstool" based toolchains for gcc-8.3 +RUN wget -O - \ + https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/8.3.0/x86_64-gcc-8.3.0-nolibc-riscv32-linux.tar.xz \ + | tar -C /opt -xJ +RUN wget -O - \ + https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/8.3.0/x86_64-gcc-8.3.0-nolibc-riscv64-linux.tar.xz \ + | tar -C /opt -xJ + +# Export the toolchains to the system path +ENV PATH="/opt/gcc-8.3.0-nolibc/riscv32-linux/bin:${PATH}" +ENV PATH="/opt/gcc-8.3.0-nolibc/riscv64-linux/bin:${PATH}" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 72f8b8aa51..b889fb96b6 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,5 +1,6 @@ include: - local: '/.gitlab-ci-edk2.yml' + - local: '/.gitlab-ci-opensbi.yml' before_script: - apt-get update -qq -- cgit v1.2.3 From c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264 Mon Sep 17 00:00:00 2001 From: Rajnesh Kanwal Date: Sun, 23 Feb 2020 15:28:06 +0500 Subject: target/riscv: Fix VS mode interrupts forwarding. Currently riscv_cpu_local_irq_pending is used to find out pending interrupt and VS mode interrupts are being shifted to represent S mode interrupts in this function. So when the cause returned by this function is passed to riscv_cpu_do_interrupt to actually forward the interrupt, the VS mode forwarding check does not work as intended and interrupt is actually forwarded to hypervisor. This patch fixes this issue. Signed-off-by: Rajnesh Kanwal Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5ea5d133aa..d3ba9efb02 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) target_ulong pending = env->mip & env->mie & ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); target_ulong vspending = (env->mip & env->mie & - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); @@ -907,6 +907,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* + * See if we need to adjust cause. Yes if its VS mode interrupt + * no if hypervisor has delegated one of hs mode's interrupt + */ + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || + cause == IRQ_VS_EXT) + cause = cause - 1; /* Trap to VS mode */ } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ -- cgit v1.2.3