slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2023-06-20	meson: Replace softmmu_ss -> system_ss	Philippe Mathieu-Daudé
2023-06-20	meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY	Philippe Mathieu-Daudé
2023-06-20	target/ppc: Check for USER_ONLY definition instead of SOFTMMU one	Philippe Mathieu-Daudé
2023-06-20	target/m68k: Check for USER_ONLY definition instead of SOFTMMU one	Philippe Mathieu-Daudé
2023-06-20	target/tricore: Remove pointless CONFIG_SOFTMMU guard	Philippe Mathieu-Daudé
2023-06-20	target/i386: Simplify i386_tr_init_disas_context()	Philippe Mathieu-Daudé
2023-06-19	target/arm: Convert load/store tags insns to decodetree	Peter Maydell
2023-06-19	target/arm: Convert load/store single structure to decodetree	Peter Maydell
2023-06-19	target/arm: Convert load/store (multiple structures) to decodetree	Peter Maydell
2023-06-19	target/arm: Convert LDAPR/STLR (imm) to decodetree	Peter Maydell
2023-06-19	target/arm: Convert load (pointer auth) insns to decodetree	Peter Maydell
2023-06-19	target/arm: Convert atomic memory ops to decodetree	Peter Maydell
2023-06-19	target/arm: Convert LDR/STR reg+reg to decodetree	Peter Maydell
2023-06-19	target/arm: Convert LDR/STR with 12-bit immediate to decodetree	Peter Maydell
2023-06-19	target/arm: Convert ld/st reg+imm9 insns to decodetree	Peter Maydell
2023-06-19	target/arm: Convert load/store-pair to decodetree	Peter Maydell
2023-06-19	target/arm: Convert load reg (literal) group to decodetree	Peter Maydell
2023-06-19	target/arm: Convert LDXP, STXP, CASP, CAS to decodetree	Peter Maydell
2023-06-19	target/arm: Convert load/store exclusive and ordered to decodetree	Peter Maydell
2023-06-19	target/arm: Convert exception generation instructions to decodetree	Peter Maydell
2023-06-19	target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree	Peter Maydell
2023-06-19	target/arm: Convert MSR (immediate) to decodetree	Peter Maydell
2023-06-19	target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree	Peter Maydell
2023-06-19	target/arm: Convert barrier insns to decodetree	Peter Maydell
2023-06-19	target/arm: Convert hint instruction space to decodetree	Peter Maydell
2023-06-19	target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores	Peter Maydell
2023-06-19	target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode	Peter Maydell
2023-06-19	target/arm: Return correct result for LDG when ATA=0	Peter Maydell
2023-06-19	target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics	Peter Maydell
2023-06-16	Merge tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu into s...	Richard Henderson
2023-06-16	target/loongarch: Fix CSR.DMW0-3.VSEG check	Jiajie Chen
2023-06-16	hw/intc: Set physical cpuid route for LoongArch ipi device	Tianrui Zhao
2023-06-15	target/arm: Allow users to set the number of VFP registers	Cédric Le Goater
2023-06-14	Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qem...	Richard Henderson
2023-06-13	target/i386: Rename helper template headers as '.h.inc'	Philippe Mathieu-Daudé
2023-06-13	target/i386/helper: Shuffle do_cpu_init()	Philippe Mathieu-Daudé
2023-06-13	target/i386/helper: Remove do_cpu_sipi() stub for user-mode emulation	Philippe Mathieu-Daudé
2023-06-13	target/hppa/meson: Only build int_helper.o with system emulation	Philippe Mathieu-Daudé
2023-06-13	target/riscv: Smepmp: Return error when access permission not allowed in PMP	Himanshu Chauhan
2023-06-13	target/riscv/vector_helper.c: Remove the check for extra tail elements	Xiao Wang
2023-06-13	target/riscv/vector_helper.c: clean up reference of MTYPE	Xiao Wang
2023-06-13	target/riscv: Fix initialized value for cur_pmmask	Weiwei Li
2023-06-13	target/riscv: Remove pc_succ_insn from DisasContext	Weiwei Li
2023-06-13	target/riscv: Enable PC-relative translation	Weiwei Li
2023-06-13	target/riscv: Use true diff for gen_pc_plus_diff	Weiwei Li
2023-06-13	target/riscv: Change gen_set_pc_imm to gen_update_pc	Weiwei Li
2023-06-13	target/riscv: Change gen_goto_tb to work on displacements	Weiwei Li
2023-06-13	target/riscv: Introduce cur_insn_len into DisasContext	Weiwei Li
2023-06-13	target/riscv: Fix target address to update badaddr	Weiwei Li
2023-06-13	target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info	Weiwei Li