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AgeCommit message (Expand)Author
2023-05-23tcg: Remove DEBUG_DISASRichard Henderson
2023-05-23qemu/atomic128: Split atomic16_readRichard Henderson
2023-05-23target/s390x: Always use cpu_atomic_cmpxchgl_be_mmu in do_csstRichard Henderson
2023-05-23target/s390x: Use cpu_{ld,st}*_mmu in do_csstRichard Henderson
2023-05-23accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmuRichard Henderson
2023-05-23target/s390x: Use tcg_gen_qemu_{ld,st}_i128 for LPQ, STPQRichard Henderson
2023-05-23target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQRichard Henderson
2023-05-19Revert "arm/kvm: add support for MTE"Peter Maydell
2023-05-18Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into stagingRichard Henderson
2023-05-18Hexagon (gdbstub): add HVX supportTaylor Simpson
2023-05-18Hexagon (gdbstub): fix p3:0 read and write via stubBrian Cain
2023-05-18Hexagon: add core gdbstub xml data for LLDBMatheus Tavares Bernardino
2023-05-18Hexagon (decode): look for pkts with multiple insns at the same slotMatheus Tavares Bernardino
2023-05-18Hexagon (iclass): update J4_hintjumpr slot constraintsMatheus Tavares Bernardino
2023-05-18Hexagon: list available CPUs with `-cpu help`Matheus Tavares Bernardino
2023-05-18Hexagon (target/hexagon/*.py): raise exception on reg parsing errorMatheus Tavares Bernardino
2023-05-18target/hexagon: fix = vs. == mishapPaolo Bonzini
2023-05-18Hexagon (target/hexagon) Additional instructions handled by idef-parserTaylor Simpson
2023-05-18Hexagon (target/hexagon) Move items to DisasContextTaylor Simpson
2023-05-18Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContextTaylor Simpson
2023-05-18Hexagon (target/hexagon) Move pred_written to DisasContextTaylor Simpson
2023-05-18Hexagon (target/hexagon) Move new_pred_value to DisasContextTaylor Simpson
2023-05-18Hexagon (target/hexagon) Move new_value to DisasContextTaylor Simpson
2023-05-18Hexagon (target/hexagon) Make special new_value for USRTaylor Simpson
2023-05-18Hexagon (target/hexagon) Add overrides for disabled idef-parser insnsTaylor Simpson
2023-05-18Hexagon (target/hexagon) Short-circuit more HVX single instruction packetsTaylor Simpson
2023-05-18Hexagon (target/hexagon) Short-circuit packet HVX writesTaylor Simpson
2023-05-18Hexagon (target/hexagon) Short-circuit packet predicate writesTaylor Simpson
2023-05-18Hexagon (target/hexagon) Short-circuit packet register writesTaylor Simpson
2023-05-18Hexagon (target/hexagon) Mark registers as read during packet analysisTaylor Simpson
2023-05-18Hexagon (target/hexagon) Don't overlap dest writes with source readsTaylor Simpson
2023-05-18Hexagon (target/hexagon) Clean up pred_written usageTaylor Simpson
2023-05-18Hexagon (target/hexagon) Eliminate uses of log_pred_write functionTaylor Simpson
2023-05-18Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch]Taylor Simpson
2023-05-18Hexagon (target/hexagon) Add overrides for clr[tf]newTaylor Simpson
2023-05-18Hexagon (target/hexagon) Add overrides for allocframe/deallocframeTaylor Simpson
2023-05-18Hexagon (target/hexagon) Add overrides for loop setup instructionsTaylor Simpson
2023-05-18Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_writeTaylor Simpson
2023-05-18Hexagon (target/hexagon) Add v73 scalar instructionsTaylor Simpson
2023-05-18Hexagon (target/hexagon) Add v69 HVX instructionsTaylor Simpson
2023-05-18Hexagon (target/hexagon) Add v68 HVX instructionsTaylor Simpson
2023-05-18Hexagon (target/hexagon) Add v68 scalar instructionsTaylor Simpson
2023-05-18Hexagon (target/hexagon) Add support for v68/v69/v71/v73Taylor Simpson
2023-05-18Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
2023-05-18target/arm: Saturate L2CTLR_EL1 core count field rather than overflowingPeter Maydell
2023-05-18target/arm: Convert ERET, ERETAA, ERETAB to decodetreePeter Maydell
2023-05-18target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetreePeter Maydell
2023-05-18target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetreePeter Maydell
2023-05-18target/arm: Convert BR, BLR, RET to decodetreePeter Maydell
2023-05-18target/arm: Convert conditional branch insns to decodetreePeter Maydell