| Age | Commit message (Expand) | Author |
|---|
| 2021-09-01 | target/arm: Implement MVE FP max/min across vector | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE fp-with-scalar VFMA, VFMAS | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE scalar fp insns | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VMAXNMA and VMINNMA | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VCMUL and VCMLA | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VFMA and VFMS | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VCADD | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VADD (floating-point) | Peter Maydell |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVV | Richard Henderson |
| 2021-09-01 | target/riscv: Tidy trans_rvh.c.inc | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVD | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVF | Richard Henderson |
| 2021-09-01 | target/riscv: Use gen_shift_imm_fn for slli_uw | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVA | Richard Henderson |
| 2021-09-01 | target/riscv: Reorg csr instructions | Richard Henderson |
| 2021-09-01 | target/riscv: Fix hgeie, hgeip | Richard Henderson |
| 2021-09-01 | target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get, dest}_gpr for integer load/store | Richard Henderson |
| 2021-09-01 | target/riscv: Use get_gpr in branches | Richard Henderson |
| 2021-09-01 | target/riscv: Use extracts for sraiw and srliw | Richard Henderson |
| 2021-09-01 | target/riscv: Use DisasExtend in shift operations | Richard Henderson |
| 2021-09-01 | target/riscv: Add DisasExtend to gen_unary | Richard Henderson |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVB | Richard Henderson |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVM | Richard Henderson |
| 2021-09-01 | target/riscv: Use gen_arith for mulh and mulhu | Richard Henderson |
| 2021-09-01 | target/riscv: Remove gen_arith_div* | Richard Henderson |
| 2021-09-01 | target/riscv: Add DisasExtend to gen_arith* | Richard Henderson |
| 2021-09-01 | target/riscv: Introduce DisasExtend and new helpers | Richard Henderson |
| 2021-09-01 | target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr | Richard Henderson |
| 2021-09-01 | target/riscv: Clean up division helpers | Richard Henderson |
| 2021-09-01 | target/riscv: Use tcg_constant_* | Richard Henderson |
| 2021-09-01 | target/riscv: Add User CSRs read-only check | LIU Zhiwei |
| 2021-09-01 | target/riscv: Don't wrongly override isa version | LIU Zhiwei |
| 2021-09-01 | target/riscv: Correct a comment in riscv_csrrw() | Bin Meng |
| 2021-08-27 | Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210827' in... | Peter Maydell |
| 2021-08-27 | Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2021-08-26' into... | Peter Maydell |
| 2021-08-27 | target/ppc: fix vector registers access in gdbstub for little-endian | Matheus Ferst |
| 2021-08-27 | target/ppc: fix vextu[bhw][lr]x helpers | Matheus Ferst |
| 2021-08-27 | ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-sav... | Cédric Le Goater |
| 2021-08-27 | ppc: Add a POWER10 DD2 CPU | Cédric Le Goater |
| 2021-08-27 | target/ppc: moved store_40x_sler to helper_regs.c | Lucas Mateus Castro (alqotel) |
| 2021-08-27 | target/ppc: moved ppc_store_sdr1 to mmu_common.c | Lucas Mateus Castro (alqotel) |
| 2021-08-27 | target/ppc: divided mmu_helper.c in 2 files | Lucas Mateus Castro (alqotel) |
| 2021-08-26 | target/arm: Do hflags rebuild in cpsr_write() | Peter Maydell |
| 2021-08-26 | target/arm: Implement HSTR.TJDBX | Peter Maydell |
| 2021-08-26 | target/arm: Implement HSTR.TTEE | Peter Maydell |
| 2021-08-26 | target/arm: Avoid assertion trying to use KVM and multiple ASes | Peter Maydell |
| 2021-08-26 | arch_init.h: Don't include arch_init.h unnecessarily | Peter Maydell |
| 2021-08-26 | target/arm/cpu64: Validate sve vector lengths are supported | Andrew Jones |
