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2021-06-21s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)David Hildenbrand
For IEEE functions, we can reuse the softfloat implementations. For the other functions, implement it generically for 32bit/64bit/128bit - carefully taking care of all weird special cases according to the tables defined in the PoP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-24-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-23-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-22-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-21-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-20-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDEDDavid Hildenbrand
128 bit -> 64 bit, there is only a single element to process. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-19-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENEDDavid Hildenbrand
64 bit -> 128 bit, there is only a single final element. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *David Hildenbrand
In addition to 32/128bit variants, we also have to support the "Signal-on-QNaN (SQ)" bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT)David Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT)David Hildenbrand
In case of 128bit, we always have a single element. Add new helpers for reading/writing 32/128 bit floats. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICALDavid Hildenbrand
Fortunately, we only need the Doubleword implementation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement VECTOR BIT PERMUTEDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify wfc64() handlingDavid Hildenbrand
... and prepare for 32/128 bit support. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vflr64() handlingDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vfll32() handlingDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vfma64() handlingDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vftci64() handlingDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vfc64() handlingDavid Hildenbrand
Pass the m5 field via simd_data() and don't provide specialized handlers for single-element variants. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vop64_2() handlingDavid Hildenbrand
Let's rework our macros and simplify. We still need helper functions in most cases due to the different parameters types. Next, we'll only have 32/128bit variants for vfi and vfsq, so special case the others. Note that for vfsq, the XxC and erm passed in the simd_data() will never be set, resulting in the same behavior. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vop64_3() handlingDavid Hildenbrand
Let's simplify, reworking our handler generation, passing the whole "m5" register content and not providing specialized handlers for "se", and reading/writing proper float64 values using new helpers. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED)David Hildenbrand
Let's use the correct name. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handlingDavid Hildenbrand
In case we encounter a NaN, we have to return the smallest possible number, corresponding to either 0 or the maximum negative number. This seems to differ from IEEE handling as implemented in softfloat, whereby we return the biggest possible number. While at it, use float32_to_uint64() in the CLGEB handler. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/kvm: remove unused gs handlingCornelia Huck
With commit 0280b3eb7c05 ("s390x/kvm: use cpu model for gscb on compat machines"), we removed any calls to kvm_s390_get_gs() in favour of a different mechanism. Let's remove the unused kvm_s390_get_gs(), and with it the now unneeded cap_gs as well. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210602125050.492500-1-cohuck@redhat.com>
2021-06-17Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell
staging * avoid deprecation warnings for SASL on macOS 10.11 or newer * fix -readconfig when config blocks have an id (like [chardev "qmp"]) * Error* initialization fixes * Improvements to ESP emulation (Mark) * Allow creating noreserve memory backends (David) * Improvements to query-memdev (David) * Bump compiler to C11 (Richard) * First round of SVM fixes from GSoC project (Lara) # gpg: Signature made Wed 16 Jun 2021 16:37:49 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (45 commits) configure: Remove probe for _Static_assert qemu/compiler: Remove QEMU_GENERIC include/qemu/lockable: Use _Generic instead of QEMU_GENERIC util: Use unique type for QemuRecMutex in thread-posix.h util: Pass file+line to qemu_rec_mutex_unlock_impl util: Use real functions for thread-posix QemuRecMutex softfloat: Use _Generic instead of QEMU_GENERIC configure: Use -std=gnu11 target/i386: Added Intercept CR0 writes check target/i386: Added consistency checks for CR0 target/i386: Added consistency checks for VMRUN intercept and ASID target/i386: Refactored intercept checks into cpu_svm_has_intercept configure: map x32 to cpu_family x86_64 for meson hmp: Print "reserve" property of memory backends with "info memdev" qmp: Include "reserve" property of memory backends hmp: Print "share" property of memory backends with "info memdev" qmp: Include "share" property of memory backends qmp: Clarify memory backend properties returned via query-memdev hostmem: Wire up RAM_NORESERVE via "reserve" property util/mmap-alloc: Support RAM_NORESERVE via MAP_NORESERVE under Linux ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-16bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operationsPeter Maydell
Currently the ARM SVE helper code defines locally some utility functions for swapping 16-bit halfwords within 32-bit or 64-bit values and for swapping 32-bit words within 64-bit values, parallel to the byte-swapping bswap16/32/64 functions. We want these also for the ARM MVE code, and they're potentially generally useful for other targets, so move them to bitops.h. (We don't put them in bswap.h with the bswap* functions because they are implemented in terms of the rotate operations also defined in bitops.h, and including bitops.h from bswap.h seems better avoided.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210614151007.4545-17-peter.maydell@linaro.org
2021-06-16target/arm: Move expand_pred_b() data to vec_helper.cPeter Maydell
For MVE, we want to re-use the large data table from expand_pred_b(). Move the data table to vec_helper.c so it is no longer in an SVE specific source file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-14-peter.maydell@linaro.org
2021-06-16target/arm: Add framework for MVE decodePeter Maydell
Add the framework for decoding MVE insns, with the necessary new files and the meson.build rules, but no actual content yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-11-peter.maydell@linaro.org
2021-06-16target/arm: Implement MVE LETP insnPeter Maydell
Implement the MVE LETP insn. This is like the existing LE loop-end insn, but it must perform an FPU-enabled check, and on loop-exit it resets LTPSIZE to 4. To accommodate the requirement to do something on loop-exit, we drop the use of condlabel and instead manage both the TB exits manually, in the same way we already do in trans_WLS(). The other MVE-specific change to the LE insn is that we must raise an INVSTATE UsageFault insn if LTPSIZE is not 4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-10-peter.maydell@linaro.org
2021-06-16target/arm: Implement MVE DLSTPPeter Maydell
Implement the MVE DLSTP insn; this is like the existing DLS insn, except that it must do an FPU access check and it sets LTPSIZE to the value specified in the insn. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-9-peter.maydell@linaro.org
2021-06-16target/arm: Implement MVE WLSTP insnPeter Maydell
Implement the MVE WLSTP insn; this is like the existing WLS insn, except that it specifies a size value which is used to set FPSCR.LTPSIZE. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-8-peter.maydell@linaro.org
2021-06-16target/arm: Implement MVE LCTPPeter Maydell
Implement the MVE LCTP instruction. We put its decode and implementation with the other low-overhead-branch insns because although it is only present if MVE is implemented it is logically in the same group as the other LOB insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-7-peter.maydell@linaro.org
2021-06-16target/arm: Let vfp_access_check() handle late NOCP checksPeter Maydell
In commit a3494d4671797c we reworked the M-profile handling of its checks for when the NOCP exception should be raised because the FPU is disabled, so that (in line with the architecture) the NOCP check is done early over a large range of the encoding space, and takes precedence over UNDEF exceptions. As part of this, we removed the code from full_vfp_access_check() which raised an exception there for M-profile with the FPU disabled, because it was no longer reachable. For MVE, some instructions which are outside the "coprocessor space" region of the encoding space must nonetheless do "is the FPU enabled" checks and possibly raise a NOCP exception. (In particular this covers the MVE-specific low-overhead branch insns LCTP, DLSTP and WLSTP.) To support these insns, reinstate the code in full_vfp_access_check(), so that their trans functions can call vfp_access_check() and get the correct behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-6-peter.maydell@linaro.org
2021-06-16target/arm: Add handling for PSR.ECI/ICIPeter Maydell
On A-profile, PSR bits [15:10][26:25] are always the IT state bits. On M-profile, some of the reserved encodings of the IT state are used to instead indicate partial progress through instructions that were interrupted partway through by an exception and can be resumed. These resumable instructions fall into two categories: (1) load/store multiple instructions, where these bits are called "ICI" and specify the register in the ldm/stm list where execution should resume. (Specifically: LDM, STM, VLDM, VSTM, VLLDM, VLSTM, CLRM, VSCCLRM.) (2) MVE instructions subject to beatwise execution, where these bits are called "ECI" and specify which beats in this and possibly also the following MVE insn have been executed. There are also a few insns (LE, LETP, and BKPT) which do not use the ICI/ECI bits but must leave them alone. Otherwise, we should raise an INVSTATE UsageFault for any attempt to execute an insn with non-zero ICI/ECI bits. So far we have been able to ignore ECI/ICI, because the architecture allows the IMPDEF choice of "always restart load/store multiple from the beginning regardless of ICI state", so the only thing we have been missing is that we don't raise the INVSTATE fault for bad guest code. However, MVE requires that we honour ECI bits and do not rexecute beats of an insn that have already been executed. Add the support in the decoder for handling ECI/ICI: * identify the ECI/ICI case in the CONDEXEC TB flags * when a load/store multiple insn succeeds, it updates the ECI/ICI state (both in DisasContext and in the CPU state), and sets a flag to say that the ECI/ICI state was handled * if we find that the insn we just decoded did not handle the ECI/ICI state, we delete all the code that we just generated for it and instead emit the code to raise the INVFAULT. This allows us to avoid having to update every non-MVE non-LDM/STM insn to make it check for "is ECI/ICI set?". We continue with our existing IMPDEF choice of not caring about the ICI state for the load/store multiples and simply restarting them from the beginning. Because we don't allow interrupts in the middle of an insn, the only way we would see this state is if the guest set ICI manually on return from an exception handler, so it's a corner case which doesn't merit optimisation. ICI update for LDM/STM is simple -- it always zeroes the state. ECI update for MVE beatwise insns will be a little more complex, since the ECI state may include information for the following insn. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-5-peter.maydell@linaro.org
2021-06-16target/arm: Handle VPR semantics in existing codePeter Maydell
When MVE is supported, the VPR register has a place on the exception stack frame in a previously reserved slot just above the FPSCR. It must also be zeroed in various situations when we invalidate FPU context. Update the code which handles the stack frames (exception entry and exit code, VLLDM, and VLSTM) to save/restore VPR. Update code which invalidates FP registers (mostly also exception entry and exit code, but also VSCCLRM and the code in full_vfp_access_check() that corresponds to the ExecuteFPCheck() pseudocode) to zero VPR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-4-peter.maydell@linaro.org
2021-06-16target/arm: Enable FPSCR.QC bit for MVEPeter Maydell
MVE has an FPSCR.QC bit similar to the A-profile Neon one; when MVE is implemented make the bit writeable, both in the generic "load and store FPSCR" helper functions and in the code for handling the NZCVQC sysreg which we had previously left as "TODO when we implement MVE". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-3-peter.maydell@linaro.org
2021-06-16target/arm: Provide and use H8 and H1_8 macrosPeter Maydell
Currently we provide Hn and H1_n macros for accessing the correct data within arrays of vector elements of size 1, 2 and 4, accounting for host endianness. We don't provide any macros for elements of size 8 because there the host endianness doesn't matter. However, this does result in awkwardness where we need to pass empty arguments to macros, because checkpatch complains about them. The empty argument is a little confusing for humans to read as well. Add H8() and H1_8() macros and use them where we were previously passing empty arguments to macros. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-2-peter.maydell@linaro.org Message-id: 20210610132505.5827-1-peter.maydell@linaro.org
2021-06-16target/arm: Fix mte page crossing testRichard Henderson
The test was off-by-one, because tag_last points to the last byte of the tag to check, thus tag_last - prev_page will equal TARGET_PAGE_SIZE when we use the first byte of the next page. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/403 Reported-by: Peter Collingbourne <pcc@google.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210612195707.840217-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-16target/i386: Added Intercept CR0 writes checkLara Lazier
When the selective CR0 write intercept is set, all writes to bits in CR0 other than CR0.TS or CR0.MP cause a VMEXIT. Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210616123907.17765-5-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-16target/i386: Added consistency checks for CR0Lara Lazier
The combination of unset CD and set NW bit in CR0 is illegal. CR0[63:32] are also reserved and need to be zero. (AMD64 Architecture Programmer's Manual, V2, 15.5) Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210616123907.17765-4-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-16target/i386: Added consistency checks for VMRUN intercept and ASIDLara Lazier
Zero VMRUN intercept and ASID should cause an immediate VMEXIT during the consistency checks performed by VMRUN. (AMD64 Architecture Programmer's Manual, V2, 15.5) Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210616123907.17765-3-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-16target/i386: Refactored intercept checks into cpu_svm_has_interceptLara Lazier
Added cpu_svm_has_intercept to reduce duplication when checking the corresponding intercept bit outside of cpu_svm_check_intercept_param Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210616123907.17765-2-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-15target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16Richard Henderson
This fprintf+assert has been in place since the beginning. It is after to the fp_access_check, so we need to move the check up. Fold that in to the pairwise filter. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210604183506.916654-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-15target/arm: Remove fprintf from disas_simd_mod_immRichard Henderson
The default of this switch is truly unreachable. The switch selector is 3 bits, and all 8 cases are present. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210604183506.916654-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-15target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16Richard Henderson
This fprintf+assert has been in place since the beginning. It is prior to the fp_access_check, so we're still good to raise sigill here. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/381 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210604183506.916654-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-08Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20210608-1' into staging Second RISC-V PR for QEMU 6.1 - Update the PLIC and CLINT DT bindings - Improve documentation for RISC-V machines - Support direct kernel boot for microchip_pfsoc - Fix WFI exception behaviour - Improve CSR printing - Initial support for the experimental Bit Manip extension # gpg: Signature made Tue 08 Jun 2021 01:28:27 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210608-1: (32 commits) target/riscv: rvb: add b-ext version cpu option target/riscv: rvb: support and turn on B-extension from command line target/riscv: rvb: add/shift with prefix zero-extend target/riscv: rvb: address calculation target/riscv: rvb: generalized or-combine target/riscv: rvb: generalized reverse target/riscv: rvb: rotate (left/right) target/riscv: rvb: shift ones target/riscv: rvb: single-bit instructions target/riscv: add gen_shifti() and gen_shiftiw() helper functions target/riscv: rvb: sign-extend instructions target/riscv: rvb: min/max instructions target/riscv: rvb: pack two words into one register target/riscv: rvb: logic-with-negate target/riscv: rvb: count bits set target/riscv: rvb: count leading/trailing zeros target/riscv: reformat @sh format encoding for B-extension target/riscv: Pass the same value to oprsz and maxsz. target/riscv/pmp: Add assert for ePMP operations target/riscv: Dump CSR mscratch/sscratch/satp ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang
Default b-ext version is v0.93. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-18-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng
B-extension is default off, use cpu rv32 or rv64 with x-b=true to enable B-extension. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210505160620.15723-17-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210505160620.15723-16-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: rvb: address calculationKito Cheng
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210505160620.15723-15-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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