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AgeCommit message (Expand)Author
2021-06-21s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)David Hildenbrand
2021-06-21s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand
2021-06-21s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDEDDavid Hildenbrand
2021-06-21s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENEDDavid Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *David Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT)David Hildenbrand
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT)David Hildenbrand
2021-06-21s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICALDavid Hildenbrand
2021-06-21s390x/tcg: Implement VECTOR BIT PERMUTEDavid Hildenbrand
2021-06-21s390x/tcg: Simplify wfc64() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vflr64() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vfll32() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vfma64() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vftci64() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vfc64() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vop64_2() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Simplify vop64_3() handlingDavid Hildenbrand
2021-06-21s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED)David Hildenbrand
2021-06-21s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handlingDavid Hildenbrand
2021-06-21s390x/kvm: remove unused gs handlingCornelia Huck
2021-06-17Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell
2021-06-16bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operationsPeter Maydell
2021-06-16target/arm: Move expand_pred_b() data to vec_helper.cPeter Maydell
2021-06-16target/arm: Add framework for MVE decodePeter Maydell
2021-06-16target/arm: Implement MVE LETP insnPeter Maydell
2021-06-16target/arm: Implement MVE DLSTPPeter Maydell
2021-06-16target/arm: Implement MVE WLSTP insnPeter Maydell
2021-06-16target/arm: Implement MVE LCTPPeter Maydell
2021-06-16target/arm: Let vfp_access_check() handle late NOCP checksPeter Maydell
2021-06-16target/arm: Add handling for PSR.ECI/ICIPeter Maydell
2021-06-16target/arm: Handle VPR semantics in existing codePeter Maydell
2021-06-16target/arm: Enable FPSCR.QC bit for MVEPeter Maydell
2021-06-16target/arm: Provide and use H8 and H1_8 macrosPeter Maydell
2021-06-16target/arm: Fix mte page crossing testRichard Henderson
2021-06-16target/i386: Added Intercept CR0 writes checkLara Lazier
2021-06-16target/i386: Added consistency checks for CR0Lara Lazier
2021-06-16target/i386: Added consistency checks for VMRUN intercept and ASIDLara Lazier
2021-06-16target/i386: Refactored intercept checks into cpu_svm_has_interceptLara Lazier
2021-06-15target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16Richard Henderson
2021-06-15target/arm: Remove fprintf from disas_simd_mod_immRichard Henderson
2021-06-15target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16Richard Henderson
2021-06-08Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...Peter Maydell
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng
2021-06-08target/riscv: rvb: address calculationKito Cheng
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