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AgeCommit message (Expand)Author
2021-01-21s390x: Use strpadcpy for copying vm nameMiroslav Rezanina
2021-01-21s390x/tcg: Ignore register content if b1/b2 is zero when handling EXECUTEDavid Hildenbrand
2021-01-21s390x/tcg: Don't ignore content in r0 when not specified via "b" or "x"David Hildenbrand
2021-01-21s390x/tcg: Fix RISBHGDavid Hildenbrand
2021-01-21s390x/tcg: Fix ALGSIDavid Hildenbrand
2021-01-19target/arm/m_helper: Silence GCC 10 maybe-uninitialized errorPhilippe Mathieu-Daudé
2021-01-19target/arm: Update REV, PUNPK for pred_descRichard Henderson
2021-01-19target/arm: Update ZIP, UZP, TRN for pred_descRichard Henderson
2021-01-19target/arm: Update PFIRST, PNEXT for pred_descRichard Henderson
2021-01-19target/arm: Introduce PREDDESC field definitionsRichard Henderson
2021-01-19target/arm: refactor vae1_tlbmask()Rémi Denis-Courmont
2021-01-19target/arm: enable Secure EL2 in max CPURémi Denis-Courmont
2021-01-19target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont
2021-01-19target/arm: revector to run-time pick target ELRémi Denis-Courmont
2021-01-19target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont
2021-01-19target/arm: secure stage 2 translation regimeRémi Denis-Courmont
2021-01-19target/arm: generalize 2-stage page-walk conditionRémi Denis-Courmont
2021-01-19target/arm: translate NS bit in page-walksRémi Denis-Courmont
2021-01-19target/arm: do S1_ptw_translate() before address space lookupRémi Denis-Courmont
2021-01-19target/arm: handle VMID change in secure stateRémi Denis-Courmont
2021-01-19target/arm: add ARMv8.4-SEL2 system registersRémi Denis-Courmont
2021-01-19target/arm: add MMU stage 1 for Secure EL2Rémi Denis-Courmont
2021-01-19target/arm: add 64-bit S-EL2 to EL exception tableRémi Denis-Courmont
2021-01-19target/arm: Define isar_feature function to test for presence of SEL2Rémi Denis-Courmont
2021-01-19target/arm: factor MDCR_EL2 common handlingRémi Denis-Courmont
2021-01-19target/arm: use arm_hcr_el2_eff() where applicableRémi Denis-Courmont
2021-01-19target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont
2021-01-19target/arm: add arm_is_el2_enabled() helperRémi Denis-Courmont
2021-01-19target/arm: remove redundant testsRémi Denis-Courmont
2021-01-19target/arm: Use object_property_add_bool for "sve" propertyRichard Henderson
2021-01-19target/arm: Add cpu properties to control pauthRichard Henderson
2021-01-19target/arm: Implement an IMPDEF pauth algorithmRichard Henderson
2021-01-18Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...Peter Maydell
2021-01-18riscv: Add semihosting supportKeith Packard
2021-01-18semihosting: Change common-semi API to be architecture-independentKeith Packard
2021-01-18semihosting: Move ARM semihosting code to shared directoriesKeith Packard
2021-01-18target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée
2021-01-18gdbstub: drop CPUEnv from gdb_exit()Alex Bennée
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng
2021-01-16target/riscv: Add CSR name in the CSR function tableBin Meng
2021-01-16target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng
2021-01-16target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra
2021-01-16gdb: riscv: Add target descriptionSylvain Pelissier
2021-01-14target/mips: Remove vendor specific CPU definitionsPhilippe Mathieu-Daudé
2021-01-14target/mips: Remove CPU_NANOMIPS32 definitionPhilippe Mathieu-Daudé
2021-01-14target/mips: Remove CPU_R5900 definitionPhilippe Mathieu-Daudé
2021-01-14target/mips: Convert Rel6 LL/SC opcodes to decodetreePhilippe Mathieu-Daudé
2021-01-14target/mips: Convert Rel6 LLD/SCD opcodes to decodetreePhilippe Mathieu-Daudé
2021-01-14target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetreePhilippe Mathieu-Daudé
2021-01-14target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetreePhilippe Mathieu-Daudé