index
:
slackcoder/qemu
master
QEMU is a generic and open source machine & userspace emulator and virtualizer
Mirror
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
Age
Commit message (
Expand
)
Author
2021-01-21
s390x: Use strpadcpy for copying vm name
Miroslav Rezanina
2021-01-21
s390x/tcg: Ignore register content if b1/b2 is zero when handling EXECUTE
David Hildenbrand
2021-01-21
s390x/tcg: Don't ignore content in r0 when not specified via "b" or "x"
David Hildenbrand
2021-01-21
s390x/tcg: Fix RISBHG
David Hildenbrand
2021-01-21
s390x/tcg: Fix ALGSI
David Hildenbrand
2021-01-19
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
Philippe Mathieu-Daudé
2021-01-19
target/arm: Update REV, PUNPK for pred_desc
Richard Henderson
2021-01-19
target/arm: Update ZIP, UZP, TRN for pred_desc
Richard Henderson
2021-01-19
target/arm: Update PFIRST, PNEXT for pred_desc
Richard Henderson
2021-01-19
target/arm: Introduce PREDDESC field definitions
Richard Henderson
2021-01-19
target/arm: refactor vae1_tlbmask()
Rémi Denis-Courmont
2021-01-19
target/arm: enable Secure EL2 in max CPU
Rémi Denis-Courmont
2021-01-19
target/arm: Implement SCR_EL2.EEL2
Rémi Denis-Courmont
2021-01-19
target/arm: revector to run-time pick target EL
Rémi Denis-Courmont
2021-01-19
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
Rémi Denis-Courmont
2021-01-19
target/arm: secure stage 2 translation regime
Rémi Denis-Courmont
2021-01-19
target/arm: generalize 2-stage page-walk condition
Rémi Denis-Courmont
2021-01-19
target/arm: translate NS bit in page-walks
Rémi Denis-Courmont
2021-01-19
target/arm: do S1_ptw_translate() before address space lookup
Rémi Denis-Courmont
2021-01-19
target/arm: handle VMID change in secure state
Rémi Denis-Courmont
2021-01-19
target/arm: add ARMv8.4-SEL2 system registers
Rémi Denis-Courmont
2021-01-19
target/arm: add MMU stage 1 for Secure EL2
Rémi Denis-Courmont
2021-01-19
target/arm: add 64-bit S-EL2 to EL exception table
Rémi Denis-Courmont
2021-01-19
target/arm: Define isar_feature function to test for presence of SEL2
Rémi Denis-Courmont
2021-01-19
target/arm: factor MDCR_EL2 common handling
Rémi Denis-Courmont
2021-01-19
target/arm: use arm_hcr_el2_eff() where applicable
Rémi Denis-Courmont
2021-01-19
target/arm: use arm_is_el2_enabled() where applicable
Rémi Denis-Courmont
2021-01-19
target/arm: add arm_is_el2_enabled() helper
Rémi Denis-Courmont
2021-01-19
target/arm: remove redundant tests
Rémi Denis-Courmont
2021-01-19
target/arm: Use object_property_add_bool for "sve" property
Richard Henderson
2021-01-19
target/arm: Add cpu properties to control pauth
Richard Henderson
2021-01-19
target/arm: Implement an IMPDEF pauth algorithm
Richard Henderson
2021-01-18
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...
Peter Maydell
2021-01-18
riscv: Add semihosting support
Keith Packard
2021-01-18
semihosting: Change common-semi API to be architecture-independent
Keith Packard
2021-01-18
semihosting: Move ARM semihosting code to shared directories
Keith Packard
2021-01-18
target/arm: use official org.gnu.gdb.aarch64.sve layout for registers
Alex Bennée
2021-01-18
gdbstub: drop CPUEnv from gdb_exit()
Alex Bennée
2021-01-16
target/riscv: Generate the GDB XML file for CSR registers dynamically
Bin Meng
2021-01-16
target/riscv: Add CSR name in the CSR function table
Bin Meng
2021-01-16
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
Bin Meng
2021-01-16
target/riscv/pmp: Raise exception if no PMP entry is configured
Atish Patra
2021-01-16
gdb: riscv: Add target description
Sylvain Pelissier
2021-01-14
target/mips: Remove vendor specific CPU definitions
Philippe Mathieu-Daudé
2021-01-14
target/mips: Remove CPU_NANOMIPS32 definition
Philippe Mathieu-Daudé
2021-01-14
target/mips: Remove CPU_R5900 definition
Philippe Mathieu-Daudé
2021-01-14
target/mips: Convert Rel6 LL/SC opcodes to decodetree
Philippe Mathieu-Daudé
2021-01-14
target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
Philippe Mathieu-Daudé
2021-01-14
target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
Philippe Mathieu-Daudé
2021-01-14
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
Philippe Mathieu-Daudé
[next]