| Age | Commit message (Expand) | Author |
|---|
| 2017-02-14 | target/openrisc: Represent MACHI:MACLO as a single unit | Richard Henderson |
| 2017-02-14 | target/openrisc: Implement msync | Richard Henderson |
| 2017-02-14 | target/openrisc: Enable trap, csync, msync, psync for user mode | Richard Henderson |
| 2017-02-14 | target/openrisc: Set flags on helpers | Richard Henderson |
| 2017-02-14 | target/openrisc: Use movcond where appropriate | Richard Henderson |
| 2017-02-14 | target/openrisc: Keep SR_CY and SR_OV in a separate variables | Richard Henderson |
| 2017-02-14 | target/openrisc: Keep SR_F in a separate variable | Richard Henderson |
| 2017-02-14 | target/openrisc: Invert the decoding in dec_calc | Richard Henderson |
| 2017-02-14 | target/openrisc: Put SR[OVE] in TB flags | Richard Henderson |
| 2017-02-14 | target/openrisc: Streamline arithmetic and OVE | Richard Henderson |
| 2017-02-14 | target/openrisc: Rationalize immediate extraction | Richard Henderson |
| 2017-02-14 | target/openrisc: Tidy insn dumping | Richard Henderson |
| 2017-02-14 | target/openrisc: Implement lwa, swa | Richard Henderson |
| 2017-02-14 | target/openrisc: Fix exception handling status registers | Stafford Horne |
| 2017-02-14 | target/openrisc: Rename the cpu from or32 to or1k | Richard Henderson |
| 2017-02-10 | target-arm: Enable vPMU support under TCG mode | Wei Huang |
| 2017-02-10 | target-arm: Add support for PMU register PMINTENSET_EL1 | Wei Huang |
| 2017-02-10 | target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0 | Wei Huang |
| 2017-02-10 | target-arm: Add support for PMU register PMSELR_EL0 | Wei Huang |
| 2017-02-07 | target/arm: A32, T32: Create Instruction Syndromes for Data Aborts | Peter Maydell |
| 2017-02-07 | target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode | Peter Maydell |
| 2017-02-07 | arm: Correctly handle watchpoints for BE32 CPUs | Julian Brown |
| 2017-02-07 | Fix Thumb-1 BE32 execution and disassembly. | Julian Brown |
| 2017-02-07 | target/arm: Add cfgend parameter for ARM CPU selection. | Julian Brown |
| 2017-02-06 | target/hppa: Fix gdb_write_register | Richard Henderson |
| 2017-02-06 | target/hppa: Tidy do_cbranch | Richard Henderson |
| 2017-02-02 | Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170202' into... | Peter Maydell |
| 2017-02-02 | ppc/kvm: Handle the "family" CPU via alias instead of registering new types | Thomas Huth |
| 2017-02-02 | target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation | Suraj Jitindar Singh |
| 2017-02-02 | target/ppc/mmu_hash64: Fix printing unsigned as signed int | Suraj Jitindar Singh |
| 2017-02-02 | tcg/POWER9: NOOP the cp_abort instruction | Suraj Jitindar Singh |
| 2017-02-02 | target/ppc/debug: Print LPCR register value if register exists | Suraj Jitindar Singh |
| 2017-02-02 | target-ppc: Add xststdc[sp, dp, qp] instructions | Nikunj A Dadhania |
| 2017-02-02 | target-ppc: Add xvtstdc[sp,dp] instructions | Nikunj A Dadhania |
| 2017-02-01 | arm: add trailing ; after MISMATCH_CHECK | Michael S. Tsirkin |
| 2017-02-01 | arm: better stub version for MISMATCH_CHECK | Michael S. Tsirkin |
| 2017-01-31 | target/ppc/cpu-models: Fix/remove bad CPU aliases | Thomas Huth |
| 2017-01-31 | target/ppc: Remove unused POWERPC_FAMILY(POWER) | Thomas Huth |
| 2017-01-31 | spapr: clock should count only if vm is running | Laurent Vivier |
| 2017-01-31 | target/ppc: Add pcr_supported to POWER9 cpu class definition | Suraj Jitindar Singh |
| 2017-01-31 | powerpc/cpu-models: rename ISAv3.00 logical PVR definition | Suraj Jitindar Singh |
| 2017-01-31 | target-ppc: Add xvcv[hpsp, sphp] instructions | Nikunj A Dadhania |
| 2017-01-31 | target-ppc: Add xsmulqp instruction | Bharata B Rao |
| 2017-01-31 | target-ppc: Add xsdivqp instruction | Bharata B Rao |
| 2017-01-31 | target-ppc: Add xscvsdqp and xscvudqp instructions | Bharata B Rao |
| 2017-01-31 | target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qp | Bharata B Rao |
| 2017-01-31 | ppc: Implement bcdutrunc. instruction | Jose Ricardo Ziviani |
| 2017-01-31 | ppc: Implement bcdtrunc. instruction | Jose Ricardo Ziviani |
| 2017-01-31 | target-ppc: Add xscvqps[d,w]z instructions | Bharata B Rao |
| 2017-01-31 | target-ppc: Add xvxsigdp instruction | Nikunj A Dadhania |
