slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2021-01-18	Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...	Peter Maydell
2021-01-18	riscv: Add semihosting support	Keith Packard
2021-01-18	semihosting: Change common-semi API to be architecture-independent	Keith Packard
2021-01-18	semihosting: Move ARM semihosting code to shared directories	Keith Packard
2021-01-18	target/arm: use official org.gnu.gdb.aarch64.sve layout for registers	Alex Bennée
2021-01-18	gdbstub: drop CPUEnv from gdb_exit()	Alex Bennée
2021-01-16	target/riscv: Generate the GDB XML file for CSR registers dynamically	Bin Meng
2021-01-16	target/riscv: Add CSR name in the CSR function table	Bin Meng
2021-01-16	target/riscv: Make csr_ops[CSR_TABLE_SIZE] external	Bin Meng
2021-01-16	target/riscv/pmp: Raise exception if no PMP entry is configured	Atish Patra
2021-01-16	gdb: riscv: Add target description	Sylvain Pelissier
2021-01-14	target/mips: Remove vendor specific CPU definitions	Philippe Mathieu-Daudé
2021-01-14	target/mips: Remove CPU_NANOMIPS32 definition	Philippe Mathieu-Daudé
2021-01-14	target/mips: Remove CPU_R5900 definition	Philippe Mathieu-Daudé
2021-01-14	target/mips: Convert Rel6 LL/SC opcodes to decodetree	Philippe Mathieu-Daudé
2021-01-14	target/mips: Convert Rel6 LLD/SCD opcodes to decodetree	Philippe Mathieu-Daudé
2021-01-14	target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree	Philippe Mathieu-Daudé
2021-01-14	target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree	Philippe Mathieu-Daudé
2021-01-14	target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree	Philippe Mathieu-Daudé
2021-01-14	target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree	Philippe Mathieu-Daudé
2021-01-14	target/mips: Convert Rel6 COP1X opcode to decodetree	Philippe Mathieu-Daudé
2021-01-14	target/mips: Convert Rel6 Special2 opcode to decodetree	Philippe Mathieu-Daudé
2021-01-14	target/mips: Remove now unreachable LSA/DLSA opcodes code	Philippe Mathieu-Daudé
2021-01-14	target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes	Philippe Mathieu-Daudé
2021-01-14	target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes	Philippe Mathieu-Daudé
2021-01-14	target/mips: Extract LSA/DLSA translation generators	Philippe Mathieu-Daudé
2021-01-14	target/mips: Use decode_ase_msa() generated from decodetree	Philippe Mathieu-Daudé
2021-01-14	target/mips: Introduce decode tree bindings for MSA ASE	Philippe Mathieu-Daudé
2021-01-14	target/mips: Pass TCGCond argument to MSA gen_check_zero_element()	Philippe Mathieu-Daudé
2021-01-14	target/mips: Extract MSA translation routines	Philippe Mathieu-Daudé
2021-01-14	target/mips: Declare gen_msa/_branch() in 'translate.h'	Philippe Mathieu-Daudé
2021-01-14	target/mips: Extract MSA helper definitions	Philippe Mathieu-Daudé
2021-01-14	target/mips: Extract MSA helpers from op_helper.c	Philippe Mathieu-Daudé
2021-01-14	target/mips: Move msa_reset() to msa_helper.c	Philippe Mathieu-Daudé
2021-01-14	target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()	Philippe Mathieu-Daudé
2021-01-14	target/mips: Remove CPUMIPSState* argument from gen_msa*() methods	Philippe Mathieu-Daudé
2021-01-14	target/mips: Extract msa_translate_init() from mips_tcg_init()	Philippe Mathieu-Daudé
2021-01-14	target/mips: Alias MSA vector registers on FPU scalar registers	Philippe Mathieu-Daudé
2021-01-14	target/mips: Remove now unused ASE_MSA definition	Philippe Mathieu-Daudé
2021-01-14	target/mips: Simplify MSA TCG logic	Philippe Mathieu-Daudé
2021-01-14	target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA	Philippe Mathieu-Daudé
2021-01-14	target/mips: Simplify msa_reset()	Philippe Mathieu-Daudé
2021-01-14	target/mips: Introduce ase_msa_available() helper	Philippe Mathieu-Daudé
2021-01-14	target/mips/translate: Expose check_mips_64() to 32-bit mode	Philippe Mathieu-Daudé
2021-01-14	target/mips/translate: Extract decode_opc_legacy() from decode_opc()	Philippe Mathieu-Daudé
2021-01-14	target/mips: Only build TCG code when CONFIG_TCG is set	Philippe Mathieu-Daudé
2021-01-14	target/mips: Extract FPU specific definitions to translate.h	Philippe Mathieu-Daudé
2021-01-14	target/mips: Declare generic FPU / Coprocessor functions in translate.h	Philippe Mathieu-Daudé
2021-01-14	target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction	Philippe Mathieu-Daudé
2021-01-14	target/mips: Replace gen_exception_err(err=0) by gen_exception_end()	Philippe Mathieu-Daudé