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path: root/target/riscv/pmp.h
AgeCommit message (Expand)Author
2024-10-30target/riscv: Introduce elp state and enabling controls for zicfilpDeepak Gupta
2024-01-10target/riscv/pmp: Use hwaddr instead of target_ulong for RV32Ivan Klokov
2023-11-07target/riscv: pmp: Clear pmp/smepmp bits on resetMayuresh Chitale
2023-06-13target/riscv: Change the return type of pmp_hart_has_privs() to boolWeiwei Li
2023-06-13target/riscv: Update pmp_get_tlb_size()Weiwei Li
2023-05-05target/riscv: Fix format for indentationWeiwei Li
2023-01-06target/riscv: Fix PMP propagation for tlbLIU Zhiwei
2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li
2022-03-06target: Include missing 'cpu.h'Philippe Mathieu-Daudé
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying
2021-03-22target/riscv: propagate PMP permission to TLB pageJim Shu
2021-01-16target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra
2020-11-03target/riscv: Add PMP state descriptionYifei Jiang
2020-08-21target/riscv: Change the TLB page size depends on PMP entries.Zong Li
2019-06-23RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary
2019-05-13Clean up ill-advised or unusual header guardsMarkus Armbruster
2018-03-07RISC-V Physical Memory ProtectionMichael Clark