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QEMU is a generic and open source machine & userspace emulator and virtualizer
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pmp.c
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Author
2024-01-10
target/riscv: pmp: Ignore writes when RW=01 and MML=0
Ivan Klokov
2024-01-10
target/riscv/pmp: Use hwaddr instead of target_ulong for RV32
Ivan Klokov
2023-11-07
target/riscv: pmp: Ignore writes when RW=01
Mayuresh Chitale
2023-11-07
target/riscv: pmp: Clear pmp/smepmp bits on reset
Mayuresh Chitale
2023-11-07
Add epmp to extensions list and rename it to smepmp
Himanshu Chauhan
2023-09-11
target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
Leon Schuermann
2023-06-13
target/riscv: Smepmp: Return error when access permission not allowed in PMP
Himanshu Chauhan
2023-06-13
target/riscv: Deny access if access is partially inside the PMP entry
Weiwei Li
2023-06-13
target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
Weiwei Li
2023-06-13
target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
Weiwei Li
2023-06-13
target/riscv: Flush TLB when pmpaddr is updated
Weiwei Li
2023-06-13
target/riscv: Update the next rule addr in pmpaddr_csr_write()
Weiwei Li
2023-06-13
target/riscv: Flush TLB when MMWP or MML bits are changed
Weiwei Li
2023-06-13
target/riscv: Remove unused paramters in pmp_hart_has_privs_default()
Weiwei Li
2023-06-13
target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled
Weiwei Li
2023-06-13
target/riscv: Change the return type of pmp_hart_has_privs() to bool
Weiwei Li
2023-06-13
target/riscv: Make the short cut really work in pmp_hart_has_privs
Weiwei Li
2023-06-13
target/riscv: Update pmp_get_tlb_size()
Weiwei Li
2023-05-05
target/riscv: Fix lines with over 80 characters
Weiwei Li
2023-05-05
target/riscv: Fix format for comments
Weiwei Li
2023-05-05
target/riscv: Fix format for indentation
Weiwei Li
2023-03-01
target/riscv: remove RISCV_FEATURE_MMU
Daniel Henrique Barboza
2023-03-01
target/riscv: remove RISCV_FEATURE_PMP
Daniel Henrique Barboza
2023-03-01
target/riscv: remove RISCV_FEATURE_EPMP
Daniel Henrique Barboza
2023-02-23
target/riscv: Smepmp: Skip applying default rules when address matches
Himanshu Chauhan
2023-01-06
target/riscv: Fix PMP propagation for tlb
LIU Zhiwei
2022-10-14
target/riscv: pmp: Fixup TLB size calculation
Alistair Francis
2022-07-03
target/riscv/pmp: guard against PMP ranges with a negative size
Nicolas Pitre
2022-04-22
target/riscv/pmp: fix NAPOT range computation overflow
Nicolas Pitre
2022-01-21
target/riscv: Adjust pmpcfg access with mxl
LIU Zhiwei
2021-07-15
target/riscv: pmp: Fix some typos
Bin Meng
2021-06-08
target/riscv/pmp: Add assert for ePMP operations
Alistair Francis
2021-05-11
target/riscv/pmp: Remove outdated comment
Alistair Francis
2021-05-11
target/riscv: Implementation of enhanced PMP (ePMP)
Hou Weiying
2021-05-11
target/riscv: Add ePMP CSR access functions
Hou Weiying
2021-05-11
target/riscv: Fix the PMP is locked check when using TOR
Alistair Francis
2021-03-22
target/riscv: flush TLB pages if PMP permission has been changed
Jim Shu
2021-03-22
target/riscv: propagate PMP permission to TLB page
Jim Shu
2021-01-16
target/riscv/pmp: Raise exception if no PMP entry is configured
Atish Patra
2020-11-03
target/riscv: Add PMP state description
Yifei Jiang
2020-08-21
target/riscv: Change the TLB page size depends on PMP entries.
Zong Li
2020-08-21
riscv: Fix bug in setting pmpcfg CSR for RISCV64
Hou Weiying
2020-07-13
target/riscv: Fix pmp NA4 implementation
Alexandre Mergnat
2020-06-19
target/riscv: Use a smaller guess size for no-MMU PMP
Alistair Francis
2019-10-28
target/riscv: PMP violation due to wrong size parameter
Dayeol Lee
2019-09-17
target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
Philippe Mathieu-Daudé
2019-09-17
target/riscv/pmp: Restrict priviledged PMP to system-mode emulation
Philippe Mathieu-Daudé
2019-06-23
RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off
Hesham Almatary
2019-06-23
RISC-V: Check for the effective memory privilege mode during PMP checks
Hesham Almatary
2019-06-23
target/riscv: Fix PMP range boundary address bug
Dayeol Lee
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