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path: root/target/riscv/op_helper.c
AgeCommit message (Expand)Author
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé
2023-08-31target/translate: Include missing 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé
2023-07-10target/riscv: Make MPV only work when MPP != PRV_MWeiwei Li
2023-05-05target/riscv: Check SUM in the correct registerRichard Henderson
2023-05-05target/riscv: Move hstatus.spvp check to check_access_hlsvRichard Henderson
2023-05-05target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BITRichard Henderson
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson
2023-05-05target/riscv: Use cpu_ld*_code_mmu for HLVXRichard Henderson
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu
2023-05-05target/riscv: fix H extension TVM trapYi Chen
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li
2023-05-05target/riscv: Fix the mstatus.MPP value after executing MRETWeiwei Li
2023-05-05target/riscv: Fix format for indentationWeiwei Li
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
2023-05-05target/riscv: Remove redundant check on RVHWeiwei Li
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner
2023-01-06target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+Bin Meng
2023-01-06target/riscv: Simplify helper_sret() a little bitBin Meng
2023-01-06target/riscv: Fix mret exception cause when no pmp rule is configuredBin Meng
2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot
2022-01-08target/riscv/pmp: fix no pmp illegal intrsNikita Shubin
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson
2021-06-08target/riscv: fix wfi exception behaviorJose Martins
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth
2021-01-16target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra
2020-11-09target/riscv: Split the Hypervisor execute load helpersAlistair Francis
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis
2020-11-09target/riscv: Set the virtualised MMU mode when doing hyp accessesAlistair Francis
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
2020-10-22target/riscv: Fix implementation of HLVX.WU instructionGeorg Kotheimer
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-03-16target/riscv: Correctly implement TSR trapAlistair Francis
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis
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