slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-11-07	target/riscv: Set vdata.vm field for vector load/store whole register instruc...	Max Chou
2024-10-30	target/riscv: implement zicfiss instructions	Deepak Gupta
2024-10-30	target/riscv: update `decode_save_opc` to store extra word2	Deepak Gupta
2024-10-30	target/riscv: zicfilp `lpad` impl and branch tracking	Deepak Gupta
2024-09-24	target/riscv: remove break after g_assert_not_reached()	Pierrick Bouvier
2024-08-06	target/riscv: Relax fld alignment requirement	LIU Zhiwei
2024-08-06	target/riscv: Add MXLEN check for F/D/Q applies to zama16b	LIU Zhiwei
2024-08-06	target/riscv: Remove redundant insn length check for zama16b	LIU Zhiwei
2024-07-18	target/riscv: Add amocas.[b\|h] for Zabha	LIU Zhiwei
2024-07-18	target/riscv: Move gen_cmpxchg before adding amocas.[b\|h]	LIU Zhiwei
2024-07-18	target/riscv: Add AMO instructions for Zabha	LIU Zhiwei
2024-07-18	target/riscv: Move gen_amo before implement Zabha	LIU Zhiwei
2024-07-18	target/riscv: Support Zama16b extension	LIU Zhiwei
2024-07-18	target/riscv: Add zcmop extension	LIU Zhiwei
2024-07-18	target/riscv: Add zimop extension	LIU Zhiwei
2024-06-03	target/riscv: rvzicbo: Fixup CBO extension register calculation	Alistair Francis
2024-06-03	target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen in...	Max Chou
2024-06-03	target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w	Max Chou
2024-06-03	target/riscv: rvv: Check single width operator for vector fp widen instructions	Max Chou
2024-06-03	target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w ins...	Max Chou
2024-06-03	target/riscv: Add support for Zve32x extension	Jason Chien
2024-06-03	trans_privileged.c.inc: set (m\|s)tval on ebreak breakpoint	Daniel Henrique Barboza
2024-06-03	target/riscv: Raise exceptions on wrs.nto	Andrew Jones
2024-03-22	target/riscv: enable 'vstart_eq_zero' in the end of insns	Ivan Klokov
2024-03-22	trans_rvv.c.inc: remove redundant mark_vs_dirty() calls	Daniel Henrique Barboza
2024-03-22	target/riscv: remove 'over' brconds from vector trans	Daniel Henrique Barboza
2024-03-22	target/riscv: always clear vstart for ldst_whole insns	Daniel Henrique Barboza
2024-03-22	target/riscv: always clear vstart in whole vec move insns	Daniel Henrique Barboza
2024-03-22	trans_rvv.c.inc: set vstart = 0 in int scalar move insns	Daniel Henrique Barboza
2024-03-08	trans_rvv.c.inc: remove 'is_store' bool from load/store fns	Daniel Henrique Barboza
2024-03-08	trans_rvv.c.inc: mark_vs_dirty() before loads and stores	Daniel Henrique Barboza
2024-03-08	RISC-V: Add support for Ztso	Palmer Dabbelt
2024-03-08	target/riscv: Update $ra with current $pc in trans_cm_jalt()	Jason Chien
2024-02-09	target/riscv: Enable xtheadsync under user mode	LIU Zhiwei
2024-02-09	target/riscv: Check 'A' and split extensions for atomic instructions	Rob Bradford
2024-02-09	trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()	Daniel Henrique Barboza
2024-02-09	target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()	Daniel Henrique Barboza
2024-02-09	target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'	Daniel Henrique Barboza
2024-02-09	target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'	Daniel Henrique Barboza
2024-02-09	target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb	Daniel Henrique Barboza
2024-02-09	target/riscv: Check for 'A' extension on all atomic instructions	Rob Bradford
2024-01-10	target/riscv: Add support for Zacas extension	Weiwei Li
2024-01-10	target/riscv: Fix th.dcache.cval1 priviledge check	LIU Zhiwei
2024-01-10	target/riscv: The whole vector register move instructions depend on vsew	Max Chou
2024-01-10	target/riscv: Add vill check for whole vector register move instructions	Max Chou
2023-11-07	target/riscv: Replace Zvbb checking by Zvkb	Max Chou
2023-11-07	target/riscv: rename ext_icboz to ext_zicboz	Daniel Henrique Barboza
2023-11-07	target/riscv: rename ext_icbom to ext_zicbom	Daniel Henrique Barboza
2023-11-07	target/riscv: rename ext_ifencei to ext_zifencei	Daniel Henrique Barboza
2023-10-03	tcg: Rename cpu_env to tcg_env	Richard Henderson