Age | Commit message (Expand) | Author |
2022-04-29 | target/riscv: rvk: add cfg properties for zbk* and zk* | Weiwei Li |
2022-04-29 | target/riscv: Support configuarable marchid, mvendorid, mipid CSR values | Frank Chang |
2022-04-22 | target/riscv: cpu: Add a config option for native debug | Bin Meng |
2022-04-22 | hw/intc: Make RISC-V ACLINT mtime MMIO register writable | Frank Chang |
2022-04-22 | target/riscv: Add initial support for the Sdtrig extension | Bin Meng |
2022-04-22 | target/riscv: Allow software access to MIP SEIP | Alistair Francis |
2022-04-22 | target/riscv: Add *envcfg* CSRs support | Atish Patra |
2022-04-22 | target/riscv: Introduce privilege version field in the CSR ops. | Atish Patra |
2022-04-22 | target/riscv: Add the privileged spec version 1.12.0 | Atish Patra |
2022-04-22 | target/riscv: Define simpler privileged spec version numbering | Atish Patra |
2022-04-21 | compiler.h: replace QEMU_NORETURN with G_NORETURN | Marc-André Lureau |
2022-04-06 | Move CPU softfloat unions to cpu-float.h | Marc-André Lureau |
2022-03-06 | target: Use ArchCPU as interface to target CPU | Philippe Mathieu-Daudé |
2022-03-06 | target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro | Philippe Mathieu-Daudé |
2022-03-06 | target: Use CPUArchState as interface to target-specific CPU state | Philippe Mathieu-Daudé |
2022-03-03 | target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} | Weiwei Li |
2022-02-16 | target/riscv: add support for svinval extension | Weiwei Li |
2022-02-16 | target/riscv: Ignore reserved bits in PTE for RV64 | Guo Ren |
2022-02-16 | target/riscv: Allow users to force enable AIA CSRs in HART | Anup Patel |
2022-02-16 | target/riscv: Implement AIA xiselect and xireg CSRs | Anup Patel |
2022-02-16 | target/riscv: Implement AIA hvictl and hviprioX CSRs | Anup Patel |
2022-02-16 | target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 | Anup Patel |
2022-02-16 | target/riscv: Implement AIA local interrupt priorities | Anup Patel |
2022-02-16 | target/riscv: Allow AIA device emulation to set ireg rmw callback | Anup Patel |
2022-02-16 | target/riscv: Add AIA cpu feature | Anup Patel |
2022-02-16 | target/riscv: Allow setting CPU feature from machine/device emulation | Anup Patel |
2022-02-16 | target/riscv: Implement hgeie and hgeip CSRs | Anup Patel |
2022-02-16 | target/riscv: Add XVentanaCondOps custom extension | Philipp Tomsich |
2022-02-16 | target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC... | Philipp Tomsich |
2022-01-21 | target/riscv: Remove VILL field in VTYPE | LIU Zhiwei |
2022-01-21 | target/riscv: Adjust vsetvl according to XLEN | LIU Zhiwei |
2022-01-21 | target/riscv: Split out the vill from vtype | LIU Zhiwei |
2022-01-21 | target/riscv: Split pm_enabled into mask and base | LIU Zhiwei |
2022-01-21 | target/riscv: Create current pm fields in env | LIU Zhiwei |
2022-01-21 | target/riscv: Create xl field in env | LIU Zhiwei |
2022-01-21 | target/riscv: rvv-1.0: Add Zve32f extension into RISC-V | Frank Chang |
2022-01-21 | target/riscv: rvv-1.0: Add Zve64f extension into RISC-V | Frank Chang |
2022-01-21 | target/riscv: Add kvm_riscv_get/put_regs_timer | Yifei Jiang |
2022-01-21 | target/riscv: Add host cpu type | Yifei Jiang |
2022-01-21 | target/riscv: Support start kernel directly by KVM | Yifei Jiang |
2022-01-08 | target/riscv: Implement the stval/mtval illegal instruction | Alistair Francis |
2022-01-08 | target/riscv: actual functions to realize crs 128-bit insns | Frédéric Pétrot |
2022-01-08 | target/riscv: helper functions to wrap calls to 128-bit csr insns | Frédéric Pétrot |
2022-01-08 | target/riscv: adding high part of some csrs | Frédéric Pétrot |
2022-01-08 | target/riscv: support for 128-bit M extension | Frédéric Pétrot |
2022-01-08 | target/riscv: setup everything for rv64 to support rv128 execution | Frédéric Pétrot |
2022-01-08 | target/riscv: array for the 64 upper bits of 128-bit registers | Frédéric Pétrot |
2021-12-20 | target/riscv: gdb: support vector registers for rv64 & rv32 | Hsiangkai Wang |
2021-12-20 | target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation | Frank Chang |