slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2020-01-15	tcg: Search includes from the project root source directory	Philippe Mathieu-Daudé
2019-10-28	target/openrisc: fetch code with translator_ld	Emilio G. Cota
2019-09-04	target/openrisc: Implement l.adrp	Richard Henderson
2019-09-04	target/openrisc: Implement unordered fp comparisons	Richard Henderson
2019-09-04	target/openrisc: Add support for ORFPX64A32	Richard Henderson
2019-09-04	target/openrisc: Check CPUCFG_OF32S for float insns	Richard Henderson
2019-09-04	target/openrisc: Cache R0 in DisasContext	Richard Henderson
2019-09-04	target/openrisc: Replace cpu register array with a function	Richard Henderson
2019-09-04	target/openrisc: Add DisasContext parameter to check_r0_write	Richard Henderson
2019-09-03	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster
2019-04-24	tcg: Hoist max_insns computation to tb_gen_code	Richard Henderson
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster
2019-01-30	target/openrisc: Fix LGPL version number	Thomas Huth
2018-10-31	decodetree: Remove "insn" argument from trans_* expanders	Richard Henderson
2018-07-03	target/openrisc: Fix cpu_mmu_index	Richard Henderson
2018-07-03	target/openrisc: Form the spr index from tcg	Richard Henderson
2018-07-03	target/openrisc: Exit the TB after l.mtspr	Richard Henderson
2018-07-03	target/openrisc: Split out is_user	Richard Henderson
2018-07-03	target/openrisc: Link more translation blocks	Richard Henderson
2018-07-03	target/openrisc: Fix singlestep_enabled	Richard Henderson
2018-07-03	target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB	Richard Henderson
2018-07-03	target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP	Richard Henderson
2018-07-03	target/openrisc: Add print_insn_or1k	Richard Henderson
2018-06-01	tcg: Pass tb and index to tcg_gen_exit_tb separately	Richard Henderson
2018-05-14	target/openrisc: Merge disas_openrisc_insn	Richard Henderson
2018-05-14	target/openrisc: Convert dec_float	Richard Henderson
2018-05-14	target/openrisc: Convert dec_compi	Richard Henderson
2018-05-14	target/openrisc: Convert dec_comp	Richard Henderson
2018-05-14	target/openrisc: Convert dec_M	Richard Henderson
2018-05-14	target/openrisc: Convert dec_logic	Richard Henderson
2018-05-14	target/openrisc: Convert dec_mac	Richard Henderson
2018-05-14	target/openrisc: Convert dec_calc	Richard Henderson
2018-05-14	target/openrisc: Convert remainder of dec_misc insns	Richard Henderson
2018-05-14	target/openrisc: Convert memory insns	Richard Henderson
2018-05-14	target/openrisc: Convert branch insns	Richard Henderson
2018-05-14	target/openrisc: Start conversion to decodetree.py	Richard Henderson
2018-05-14	target-openrisc: Write back result before FPE exception	Richard Henderson
2018-05-09	target/openrisc: convert to TranslatorOps	Emilio G. Cota
2018-05-09	target/openrisc: convert to DisasContextBase	Emilio G. Cota
2017-10-27	Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging	Peter Maydell
2017-10-25	disas: Remove unused flags arguments	Richard Henderson
2017-10-24	tcg: Initialize cpu_env generically	Richard Henderson
2017-10-24	tcg: define tcg_init_ctx and make tcg_ctx a pointer	Emilio G. Cota
2017-10-24	tcg: convert tb->cflags reads to tb_cflags(tb)	Emilio G. Cota
2017-09-06	target: [tcg] Use a generic enum for DISAS_ values	Lluís Vilanova
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova
2017-05-04	target/openrisc: implement shadow registers	Stafford Horne
2017-02-14	target/openrisc: Optimize for r0 being zero	Richard Henderson
2017-02-14	target/openrisc: Tidy handling of delayed branches	Richard Henderson