slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2018-10-29	target/mips: Add emulation of non-MXU MULL within MXU decoding engine	Craig Janeczek
2018-10-29	target/mips: Add bit encoding for MXU operand getting pattern 'optn3'	Craig Janeczek
2018-10-29	target/mips: Add bit encoding for MXU operand getting pattern 'optn2'	Craig Janeczek
2018-10-29	target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'	Aleksandar Markovic
2018-10-29	target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'	Craig Janeczek
2018-10-29	target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'	Aleksandar Markovic
2018-10-29	target/mips: Add MXU decoding engine	Aleksandar Markovic
2018-10-29	target/mips: Add and integrate MXU decoding engine placeholder	Aleksandar Markovic
2018-10-29	target/mips: Amend MXU instruction opcodes	Aleksandar Markovic
2018-10-29	target/mips: Define a bit for MXU in insn_flags	Craig Janeczek
2018-10-29	target/mips: Introduce MXU registers	Craig Janeczek
2018-10-29	target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases	Aleksandar Markovic
2018-10-25	target/mips: Add disassembler support for nanoMIPS	Aleksandar Markovic
2018-10-25	target/mips: Implement emulation of nanoMIPS EVA instructions	Dimitrije Nikolic
2018-10-25	target/mips: Add nanoMIPS CRC32 instruction pool	Aleksandar Markovic
2018-10-24	target/mips: Fix decoding of ALIGN and DALIGN instructions	Aleksandar Markovic
2018-10-24	target/mips: Fix the title of translate.c	Aleksandar Markovic
2018-10-24	target/mips: Define the R5900 CPU	Fredrik Noring
2018-10-24	target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only	Fredrik Noring
2018-10-24	target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV	Fredrik Noring
2018-10-24	target/mips: Support R5900 DIV1 and DIVU1 instructions	Fredrik Noring
2018-10-24	target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions	Fredrik Noring
2018-10-24	target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions	Fredrik Noring
2018-10-24	target/mips: Support R5900 three-operand MULT and MULTU instructions	Fredrik Noring
2018-10-24	target/mips: Add a placeholder for R5900 MMI3 instruction subclass	Fredrik Noring
2018-10-24	target/mips: Add a placeholder for R5900 MMI2 instruction subclass	Fredrik Noring
2018-10-24	target/mips: Add a placeholder for R5900 MMI1 instruction subclass	Fredrik Noring
2018-10-24	target/mips: Add a placeholder for R5900 MMI0 instruction subclass	Fredrik Noring
2018-10-24	target/mips: Add a placeholder for R5900 MMI instruction class	Fredrik Noring
2018-10-24	target/mips: Add a placeholder for R5900 LQ	Fredrik Noring
2018-10-24	target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR	Fredrik Noring
2018-10-24	target/mips: Define R5900 MMI3 opcode constants	Fredrik Noring
2018-10-24	target/mips: Define R5900 MMI2 opcode constants	Fredrik Noring
2018-10-24	target/mips: Define R5900 MMI1 opcode constants	Fredrik Noring
2018-10-24	target/mips: Define R5900 MMI0 opcode constants	Fredrik Noring
2018-10-24	target/mips: Define R5900 MMI<0\|1\|2\|3> subclasses and opcode constants	Fredrik Noring
2018-10-24	target/mips: Define R5900 MMI class, and LQ and SQ opcode constants	Fredrik Noring
2018-10-24	target/mips: Add R5900 Multimedia Instruction overview note	Fredrik Noring
2018-10-24	target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants	Fredrik Noring
2018-10-18	target/mips: Add opcodes for nanoMIPS EVA instructions	Dimitrije Nikolic
2018-10-18	target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH	Stefan Markovic
2018-10-18	target/mips: Fix emulation of microMIPS R6 <SELEQZ\|SELNEZ>.<D\|S>	Matthew Fortune
2018-10-18	target/mips: Implement hardware page table walker for MIPS32	Yongbok Kim
2018-10-18	target/mips: Add reset state for PWSize and PWField registers	Yongbok Kim
2018-10-18	target/mips: Add CP0 PWCtl register	Yongbok Kim
2018-10-18	target/mips: Add CP0 PWSize register	Yongbok Kim
2018-10-18	target/mips: Add CP0 PWField register	Yongbok Kim
2018-10-18	target/mips: Add CP0 PWBase register	Yongbok Kim
2018-10-18	target/mips: Add CP0 Config2 to DisasContext	Stefan Markovic
2018-10-18	target/mips: Improve DSP R2/R3-related naming	Stefan Markovic