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AgeCommit message (Expand)Author
2012-06-10target-xtensa: remove unnecessary include of dyngen-exec.hPeter Portante
2012-06-09target-xtensa: fix CCOUNT for conditional branchesMax Filippov
2012-06-09target-xtensa: control page table lookup explicitlyMax Filippov
2012-06-09target-xtensa: update autorefill TLB entries conditionallyMax Filippov
2012-06-09target-xtensa: extract TLB entry setting methodMax Filippov
2012-06-09target-xtensa: update EXCVADDR in case of page table lookupMax Filippov
2012-06-09target-xtensa: flush TLB page for new MMU mappingMax Filippov
2012-06-07build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini
2012-06-07build: move libobj-y variable to nested Makefile.objsPaolo Bonzini
2012-06-07build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini
2012-06-04Kill off cpu_state_reset()Andreas Färber
2012-06-04target-xtensa: Let cpu_xtensa_init() return XtensaCPUAndreas Färber
2012-04-21target-xtensa: fix LOOPNEZ/LOOPGTZ translationMax Filippov
2012-04-15target-xtensa: add license to core-fsf.cMax Filippov
2012-04-15target-xtensa: add license to core-dc232b.cMax Filippov
2012-04-15target-xtensa: add dc233c coreMax Filippov
2012-04-14target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov
2012-04-14Use uintptr_t for various op related functionsBlue Swirl
2012-04-14target-xtensa: Start QOM'ifying CPU initAndreas Färber
2012-04-14target-xtensa: QOM'ify CPU resetAndreas Färber
2012-04-14target-xtensa: QOM'ify CPUAndreas Färber
2012-04-14target-xtensa: Move helpers.h to helper.hLluís Vilanova
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber
2012-03-03Merge branch 'upstream' of git://qemu.weilnetz.de/qemuBlue Swirl
2012-02-28target-xtensa: Clean includesStefan Weil
2012-02-20target-xtensa: add DEBUG_SECTION to overlay toolMax Filippov
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov
2012-02-18target-xtensa: fetch 3rd opcode byte only when neededMax Filippov
2012-02-18target-xtensa: implement info tlb monitor commandMax Filippov
2012-02-18target-xtensa: define TLB_TEMPLATE for MMU-less coresMax Filippov
2011-11-26target-xtensa: fix MMUv3 initializationMax Filippov
2011-11-02target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov
2011-11-02target-xtensa: handle cache options in the overlay toolMax Filippov
2011-11-02target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov
2011-10-16target-xtensa: add fsf coreMax Filippov
2011-10-16target-xtensa: add dc232b coreMax Filippov
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov
2011-10-16target-xtensa: remove hand-written xtensa cores implementationsMax Filippov
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov
2011-10-15target-xtensa: implement MAC16 optionMax Filippov
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl
2011-09-10target-xtensa: add dc232b core and boardMax Filippov
2011-09-10target-xtensa: implement boolean optionMax Filippov
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