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AgeCommit message (Expand)Author
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber
2012-03-03Merge branch 'upstream' of git://qemu.weilnetz.de/qemuBlue Swirl
2012-02-28target-xtensa: Clean includesStefan Weil
2012-02-20target-xtensa: add DEBUG_SECTION to overlay toolMax Filippov
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov
2012-02-18target-xtensa: fetch 3rd opcode byte only when neededMax Filippov
2012-02-18target-xtensa: implement info tlb monitor commandMax Filippov
2012-02-18target-xtensa: define TLB_TEMPLATE for MMU-less coresMax Filippov
2011-11-26target-xtensa: fix MMUv3 initializationMax Filippov
2011-11-02target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov
2011-11-02target-xtensa: handle cache options in the overlay toolMax Filippov
2011-11-02target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov
2011-10-16target-xtensa: add fsf coreMax Filippov
2011-10-16target-xtensa: add dc232b coreMax Filippov
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov
2011-10-16target-xtensa: remove hand-written xtensa cores implementationsMax Filippov
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov
2011-10-15target-xtensa: implement MAC16 optionMax Filippov
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl
2011-09-10target-xtensa: add dc232b core and boardMax Filippov
2011-09-10target-xtensa: implement boolean optionMax Filippov
2011-09-10target-xtensa: implement memory protection optionsMax Filippov
2011-09-10target-xtensa: add gdb supportMax Filippov
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov
2011-09-10target-xtensa: implement accurate window checkMax Filippov
2011-09-10target-xtensa: implement interrupt optionMax Filippov
2011-09-10target-xtensa: implement SIMCALLMax Filippov
2011-09-10target-xtensa: implement unaligned exception optionMax Filippov
2011-09-10target-xtensa: implement extended L32RMax Filippov
2011-09-10target-xtensa: implement loop optionMax Filippov
2011-09-10target-xtensa: implement windowed registersMax Filippov
2011-09-10target-xtensa: implement RST2 group (32 bit mul/div/rem)Max Filippov
2011-09-10target-xtensa: implement exceptionsMax Filippov
2011-09-10target-xtensa: add PS register and access controlMax Filippov
2011-09-10target-xtensa: implement CACHE groupMax Filippov
2011-09-10target-xtensa: implement SYNC groupMax Filippov
2011-09-10target-xtensa: mark reserved and TBD opcodesMax Filippov
2011-09-10target-xtensa: implement LSAI groupMax Filippov
2011-09-10target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov
2011-09-10target-xtensa: implement RST3 groupMax Filippov
2011-09-10target-xtensa: add special and user registersMax Filippov
2011-09-10target-xtensa: implement JX/RET0/CALLXMax Filippov
2011-09-10target-xtensa: implement conditional jumpsMax Filippov
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