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path: root/target-sparc/translate.c
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2016-12-20Move target-* CPU file into a target/ folderThomas Huth
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-11-01log: Add locking to large logging blocksRichard Henderson
Reuse the existing locking provided by stdio to keep in_asm, cpu, op, op_opt, op_ind, and out_asm as contiguous blocks. While it isn't possible to interleave e.g. in_asm or op_opt logs because of the TB lock protecting all code generation, it is possible to interleave cpu logs, or to interleave a cpu dump with an out_asm dump. For mingw32, we appear to have no viable solution for this. The locking functions are not properly exported from the system runtime library. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Use tcg_gen_atomic_cmpxchg_tlRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Use tcg_gen_atomic_xchg_tlRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Allow 4-byte alignment on fp mem opsRichard Henderson
The cpu is allowed to require stricter alignment on these 8- and 16-byte operations, and the OS is required to fix up the accesses as necessary, so the previous code was not wrong. However, we can easily handle this misalignment for all direct 8-byte operations and for direct 16-byte loads. We must retain 16-byte alignment for 16-byte stores, so that we don't have to probe for writability of a second page before performing the first of two 8-byte stores. We also retain 8-byte alignment for no-fault loads, since they are rare and it's not worth extending the helpers for this. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Implement ldqf and stqf inlineRichard Henderson
At the same time, fix a problem with stqf_asi, when a write might access two pages. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Remove asi helper code handled inlineRichard Henderson
Now that we never call out to helpers when direct accesses can handle an asi, remove the corresponding code in those helpers. For ldda, this removes the entire helper. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Implement BCOPY/BFILL inlineRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Implement cas_asi/casx_asi inlineRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Implement ldstub_asi inlineRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Implement swap_asi inlineRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Handle more twinx asisRichard Henderson
As used by HelenOS, presumably for ultra 2 and 3, prior to the sun4v platform and the current twinx names. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Use MMU_PHYS_IDX for bypass asisRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Introduce cpu_raise_exception_raRichard Henderson
Several helpers call helper_raise_exception directly, which requires in turn that their callers have performed save_state. The new function allows a TCG return address to be passed in so that we can restore PC + NPC + flags data from that. This fixes a bug in the usage of helper_check_align, whose callers had not been calling save_state. It fixes another bug in which the divide helpers used GETPC at a level other than the direct callee from TCG. This allows the translator to avoid save_state prior to SAVE, RESTORE, and FLUSHW instructions. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-31target-sparc: Use overalignment flags for twinx and block asisRichard Henderson
This allows us to enforce 16 and 64-byte alignment without any extra overhead. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1466744068-6615-1-git-send-email-rth@twiddle.net>
2016-07-12target-sparc: Elide duplicate updates to fprsRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Use cpu_loop_exit_restore from helper_check_ieee_exceptionsRichard Henderson
This avoids needing to save state before every FP operation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Use cpu_fsr in stfsrRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Use explicit writes to cpu_fsrRichard Henderson
By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Remove helper_ldf_asi, helper_stf_asiRichard Henderson
We've now implemented all fp asis inline, except for the no-fault memory reads. The latter can be passed directly to helper_ld_asi. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Directly implement block and short ldf/stf asisRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Directly implement easy ldf/stf asisRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Pass TCGMemOp constants to helper_ld/st_asiRichard Henderson
Reduces the argument count for helper_ld_asi; do helper_st_asi for consistency. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Directly implement easy ldd/std asisRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Introduce gen_check_alignRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Use QT0 to return results from lddaRichard Henderson
Also implement a few more twinx asis. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Directly implement easy ld/st asisRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Use defines from asi.hRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Pass TCGMemOp to gen_ld/st_asiRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Introduce get_asiRichard Henderson
Replace gen_get_asi, and use it for both 32-bit and 64-bit. For v8, do supervisor and immediate checks here. Also, move save_state and TB ending into the respective subroutines, out of disas_sparc_insn. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Store %asi in TB flagsRichard Henderson
Knowing the value of %asi at translation time means that we can handle the common settings without a function call. The steady state appears to be %asi == ASI_P, so that sparcv9 code can use offset forms of lda/sta. The %asi register gets pushed and popped on entry to certain functions, but it rarely takes on values other than ASI_P or ASI_AIUP. Therefore we're unlikely to be expanding the set of TBs created. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Unify asi handling between 32 and 64-bitRichard Henderson
We now have a single copy of gen_ld_asi, gen_st_asi, gen_swap_asi, and everything uses gen_get_asi. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Create gen_exceptionRichard Henderson
This unifies quite a few duplicate code fragments. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Store mmu index in TB flagsRichard Henderson
Doing this instead of saving the raw PS_PRIV and TL. This means that all nucleus mode TBs (TL > 0) can be shared. This fixes a bug in that we didn't include HS_PRIV in the TB flags, and so could produce incorrect TB matches for hypervisor state. The LSU and DMMU states were unused by the translator. Including them in TB flags meant unnecessary mismatches from tb_find_fast. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-sparc: Remove softint as a TCG globalRichard Henderson
The global is only ever read for one insn; we can just as well use a load from env instead and generate the same code. This also allows us to indicate the the associated helpers do not touch TCG globals. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-06-24target-sparc: fix register corruption in ldstub if there is no write permissionArtyom Tarasenko
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova
Information is tracked inside the TCGContext structure, and later used by tracing events with the 'tcg' and 'vcpu' properties. The 'cpu' field is used to check tracing of translation-time events ("*_trans"). The 'tcg_env' field is used to pass it to execution-time events ("*_exec"). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 146549350162.18437.3033661139638458143.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-05target-*: dfilter support for in_asmRichard Henderson
The arm target was handled by 06486077, but other targets were ignored. This handles all the rest which actually support disassembly (that is, skipping moxie and tilegx). Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini
exec-all.h contains TCG-specific definitions. It is not needed outside TCG-specific files such as translate.c, exec.c or *helper.c. One generic function had snuck into include/exec/exec-all.h; move it to include/qom/cpu.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov
In user mode, there's only a static address translation, TBs are always invalidated properly and direct jumps are reset when mapping change. Thus the destination address is always valid for direct jumps and there's no need to restrict it to the pages the TB resides in. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-04-11target-sparc: fix ldstub sign-extension bugMark Cave-Ayland
ldstub [addr], reg incorrectly reads a signed byte from memory which causes problems in the 32-bit Solaris mutex code. Here the byte value being read is 0xff which is incorrectly sign-extended to 0xffffffff before being written back to the target register causing lock detection to behave incorrectly. This fixes the intermittent hangs and MUTEX_HELD warnings issued to the console when running 32-bit Solaris images under qemu-system-sparc. With thanks to Joseph Dery for providing a condensed test image to consistently reproduce the problem on demand, and Martin Husemann for allowing me access to real hardware for comparison. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-By: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2016-03-01tcg: Add type for vCPU pointersLluís Vilanova
Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The tracing infrastructure later needs to differentiate between regular pointers and pointers to vCPUs. Also changes all targets to use the new 'TCGv_env' type instead of the generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env' translates into 'TCGv_ptr'), but that could change in the future to enforce the difference. Note that a 'TCGv_env' type (for 'CPUState') is not added, since all helpers currently receive the architecture-specific pointer ('CPUArchState'). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Acked-by: Richard Henderson <rth@twiddle.net> Message-id: 145641859552.30295.7821536833590725201.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-02-23target-sparc: Use global registers for the register windowRichard Henderson
Via indirection off cpu_regwptr. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-23target-sparc: Tidy global register initializationRichard Henderson
Create tables for the various global registers that need allocation. Remove one level of indirection from gregnames and fregnames. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson
Thus, use cpu_env as the parameter, not TCG_AREG0 directly. Update all uses in the translators. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini
Split the bits that require it to exec/log.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-id: 1452174932-28657-8-git-send-email-den@openvz.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-01-29sparc: Clean up includesPeter Maydell
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-7-git-send-email-peter.maydell@linaro.org
2016-01-07target-sparc: implement NPT timer bitMark Cave-Ayland
If the NPT bit is set in the timer register, all non-supervisor read accesses to the register should fail with a privilege exception. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-By: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2015-12-10sparc: allow CASA with ASI 0xa from user spaceAlex Zuepke
LEON3 allows the CASA instruction to be used from user space if the ASI is set to 0xa (user data). Signed-off-by: Alex Zuepke <azu@sysgo.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson
Some targets already had this within their logic, but make sure it's present for all targets. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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