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path: root/target-sparc/cpu.h
AgeCommit message (Expand)Author
2008-11-18Refactor translation block CPU state handling (Jan Kiszka)aliguori
2008-11-18Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)aliguori
2008-10-06Show size for unassigned accesses (Robert Reif)blueswir1
2008-10-03Rearrange tick functionsblueswir1
2008-10-03Fix missing prototype warnings by moving declarationsblueswir1
2008-09-22Add software and timer interrupt supportblueswir1
2008-09-20Move signal handler prototype back to cpu.hblueswir1
2008-09-10Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir1
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir1
2008-09-06Silence gcc warning about constant overflowblueswir1
2008-08-29Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir1
2008-08-29Fix Sparc64 boot on i386 host:blueswir1
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir1
2008-07-25Make MAXTL dynamic, bounds check tl when indexingblueswir1
2008-07-24Sparc32: save/load all MMU registers, Sparc64: add CPU save/loadblueswir1
2008-07-21Use MMU globals for some MMU trapsblueswir1
2008-07-20Make UA200x features selectable, add MMU typesblueswir1
2008-07-16Fix MMU miss trapsblueswir1
2008-07-01Move interrupt_request and user_mode_only to common cpu state.pbrook
2008-06-30Move CPU save/load registration to common code.pbrook
2008-06-29Add instruction counter.pbrook
2008-06-23Fix compiler warning (Jan Kiszka)blueswir1
2008-06-07Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir1
2008-05-30Fix typo.pbrook
2008-05-30Move clone() register setup to target specific code. Handle fork-like clone.pbrook
2008-05-29MicroSparc I didn't have fsmuld opblueswir1
2008-05-29Push common interrupt variables to cpu-defs.h (Glauber Costa)bellard
2008-05-28moved halted field to CPU_COMMONbellard
2008-05-12Wrap long linesblueswir1
2008-05-10Remove duplicated fieldblueswir1
2008-05-10suppressed fixed registersbellard
2008-05-10Fix compiler warningsblueswir1
2008-05-09CPU feature selection supportblueswir1
2008-05-04Complete the TCG conversionblueswir1
2008-04-23Document the shift valuesblueswir1
2008-03-29 Move CPU stuff unrelated to translation to helper.cblueswir1
2008-03-16 Convert mulscc to TCG, add cc_src2blueswir1
2008-03-13 Convert condition code changing versions of add, sub, logic, and div to TCGblueswir1
2008-03-06 Convert exception ops to TCGblueswir1
2008-03-05 Convert Sparc64 trap state ops to TCGblueswir1
2008-03-02 Convert tick operations to TCGblueswir1
2008-02-14 Fix remote debugger memory access problems reported by Matthias Steinblueswir1
2008-02-11 Sparc32 MMU register fixes (Robert Reif)blueswir1
2007-11-28Use slavio base as boot prom address, rearrange sun4m init codeblueswir1
2007-11-25 128-bit float support for user modeblueswir1
2007-11-25 More MMU registers (Robert Reif)blueswir1
2007-11-10added cpu_model parameter to cpu_init()bellard
2007-11-07 CPU specific boot mode (Robert Reif)blueswir1
2007-10-14 Sparc64 hypervisor modeblueswir1
2007-10-14 SuperSparc MXCC support (Robert Reif)blueswir1