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path: root/target-mips/op.c
AgeCommit message (Expand)Author
2007-06-23Handle MIPS64 SEGBITS value correctly.ths
2007-06-22Fix write to K0 bits in Config0, by Aurelien Jarno.ths
2007-05-29Don't check the FPU state for each FPU instruction, use hflags toths
2007-05-28Handle PX/UX status flags correctly, by Aurelien Jarno.ths
2007-05-28MIPS64 addressing fixes, by Aurelien Jarno.ths
2007-05-23The 24k wants more watch and srsmap registers.ths
2007-05-23The previous patch to make breakpoints work was a performanceths
2007-05-20Fix indexed FP load/store instructions.ths
2007-05-19More MIPS 64-bit FPU support.ths
2007-05-19Fix slti/sltiu for MIPS64, by Aurelien Jarno.ths
2007-05-18- Move FPU exception handling into helper functions, since they are big.ths
2007-05-18Work around the lack of proper handling for self-modifying code.ths
2007-05-16More generic 64 bit multiplication support, by Aurelien Jarno.ths
2007-05-13Full MIPS64 MMU implementation, by Aurelien Jarno.ths
2007-05-13Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno.ths
2007-05-13Delete misleading comment.ths
2007-05-13MMU code improvements, by Aurelien Jarno.ths
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths
2007-05-11Implemented cabs FP instructions, and improve exception handling forths
2007-05-11Implement FP madd/msub, wire up bc1any[24][ft].ths
2007-05-09Fix MIPS64 address computation specialcase, by Aurelien Jarno.ths
2007-05-08Work around gcc's mips define, spotted by Stefan Weil.ths
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths
2007-04-15Don't use T2 for INS, it conflicts with branch delay slot handling.ths
2007-04-15Fix qemu SIGFPE caused by division-by-zero due to underflow.ths
2007-04-14Restart interrupts after an exception.ths
2007-04-13Another fix for CP0 Cause register handling.ths
2007-04-11More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths
2007-04-09Fix CP0_IntCtl handling.ths
2007-04-09Proper handling of reserved bits in the context register.ths
2007-04-09Mark watchpoint features as unimplemented.ths
2007-04-09Fix exception handling cornercase for rdhwr.ths
2007-04-07Fix ins/ext cornercase.ths
2007-04-06Save state for all CP0 instructions, they may throw a CPU exception.ths
2007-04-05Fix rotr immediate ops, mask shift/rotate arguments to their allowedths
2007-04-05Fix RDHWR handling. Code formatting. Don't use *_direct versions to raiseths
2007-04-01Actually enable 64bit configuration.ths
2007-03-30Sanitize mips exception handling.ths
2007-03-23Fix enough FPU/R2 support to get 24Kf going.ths
2007-03-18Fix BD flag handling, cause register contents, implement some more bitsths
2007-03-02MIPS Userland TLS register emulation, by Daniel Jacobowitz.ths
2007-02-28MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths
2007-02-27Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.ths
2007-02-18Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths
2007-01-24EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.ths
2007-01-24Reworking MIPS interrupt handling, by Aurelien Jarno.ths
2007-01-23Implementing dmfc/dmtc.ths
2007-01-01Fix bad data type.ths
2006-12-21Scrap SIGN_EXTEND32.ths