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path: root/target-mips/op.c
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2007-11-09Use FORCE_RET, scrap RETURN which was implemented in target-specific code.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3560 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-08Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths
defines for linux-user. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3556 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29Restrict CP0_PerfCnt to legal values.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3476 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-28Implement missing MIPS supervisor mode bits.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3472 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27Add sharable clz/clo inline functions and use them for the mips target.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3455 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-26The other half of the mul64 rework. Sorry for the breakage, I committedths
an incomplete version of what I tested. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3454 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-24Force proper sign extension for mfc0/mfhc0 on MIPS64.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3432 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-23Fix writable length of the index register.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3431 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-23Fix CLO calculation for MIPS64. And a small code cleanup.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3428 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-09Use always_inline in the MIPS support where applicable.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3375 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-30Code provision for n32/n64 mips userland emulation. Not functional yet.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3284 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-26hflags computation cleanup, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3243 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-25Timer start/stop implementation, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3237 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-25Optimise instructions accessing CP0, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3235 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-24Per-CPU instruction decoding implementation, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3228 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-06Partial support for 34K multithreading, not functional yet.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3156 c046a42c-6fe2-441c-8c8c-71466251a162
2007-08-26Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3146 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-25MIPS64 improvements, based on a patch by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3021 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-23Handle MIPS64 SEGBITS value correctly.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3011 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-22Fix write to K0 bits in Config0, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3006 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-29Don't check the FPU state for each FPU instruction, use hflags toths
handle this per-tb. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2896 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-28Handle PX/UX status flags correctly, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2892 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-28MIPS64 addressing fixes, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2888 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-23The 24k wants more watch and srsmap registers.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2849 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-23The previous patch to make breakpoints work was a performanceths
disaster, use a similiar hack as ARM does instead. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2848 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-20Fix indexed FP load/store instructions.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2837 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-19More MIPS 64-bit FPU support.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2834 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-19Fix slti/sltiu for MIPS64, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2833 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-18- Move FPU exception handling into helper functions, since they are big.ths
- Fix FP-conditional branches. - Check FPU register mode at runtime, not translation time, as the F64 status bit can change. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2828 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-18Work around the lack of proper handling for self-modifying code.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2827 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-16More generic 64 bit multiplication support, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2821 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13Full MIPS64 MMU implementation, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2820 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2819 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13Delete misleading comment.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2814 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13MMU code improvements, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2811 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2809 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-11Implemented cabs FP instructions, and improve exception handling forths
trunc/floor/ceil/round. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2804 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-11Implement FP madd/msub, wire up bc1any[24][ft].ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2802 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-09Fix MIPS64 address computation specialcase, by Aurelien Jarno.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2793 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-08Work around gcc's mips define, spotted by Stefan Weil.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2786 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths
conditional branch handling. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2779 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-15Don't use T2 for INS, it conflicts with branch delay slot handling.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2674 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-15Fix qemu SIGFPE caused by division-by-zero due to underflow.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2673 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-14Restart interrupts after an exception.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2664 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-13Another fix for CP0 Cause register handling.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2658 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-11More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths
end up empty for 32bit mips, which dyngen trips over. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2648 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09Fix CP0_IntCtl handling.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2645 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09Proper handling of reserved bits in the context register.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2644 c046a42c-6fe2-441c-8c8c-71466251a162
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