| Age | Commit message (Expand) | Author |
|---|
| 2007-05-13 | Full MIPS64 MMU implementation, by Aurelien Jarno. | ths |
| 2007-05-13 | Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno. | ths |
| 2007-05-13 | Delete misleading comment. | ths |
| 2007-05-13 | MMU code improvements, by Aurelien Jarno. | ths |
| 2007-05-13 | MIPS TLB style selection at runtime, by Herve Poussineau. | ths |
| 2007-05-11 | Implemented cabs FP instructions, and improve exception handling for | ths |
| 2007-05-11 | Implement FP madd/msub, wire up bc1any[24][ft]. | ths |
| 2007-05-09 | Fix MIPS64 address computation specialcase, by Aurelien Jarno. | ths |
| 2007-05-08 | Work around gcc's mips define, spotted by Stefan Weil. | ths |
| 2007-05-07 | MIPS 64-bit FPU support, plus some collateral bugfixes in the | ths |
| 2007-04-17 | Choose number of TLBs at runtime, by Herve Poussineau. | ths |
| 2007-04-15 | Don't use T2 for INS, it conflicts with branch delay slot handling. | ths |
| 2007-04-15 | Fix qemu SIGFPE caused by division-by-zero due to underflow. | ths |
| 2007-04-14 | Restart interrupts after an exception. | ths |
| 2007-04-13 | Another fix for CP0 Cause register handling. | ths |
| 2007-04-11 | More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may | ths |
| 2007-04-09 | Fix CP0_IntCtl handling. | ths |
| 2007-04-09 | Proper handling of reserved bits in the context register. | ths |
| 2007-04-09 | Mark watchpoint features as unimplemented. | ths |
| 2007-04-09 | Fix exception handling cornercase for rdhwr. | ths |
| 2007-04-07 | Fix ins/ext cornercase. | ths |
| 2007-04-06 | Save state for all CP0 instructions, they may throw a CPU exception. | ths |
| 2007-04-05 | Fix rotr immediate ops, mask shift/rotate arguments to their allowed | ths |
| 2007-04-05 | Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise | ths |
| 2007-04-01 | Actually enable 64bit configuration. | ths |
| 2007-03-30 | Sanitize mips exception handling. | ths |
| 2007-03-23 | Fix enough FPU/R2 support to get 24Kf going. | ths |
| 2007-03-18 | Fix BD flag handling, cause register contents, implement some more bits | ths |
| 2007-03-02 | MIPS Userland TLS register emulation, by Daniel Jacobowitz. | ths |
| 2007-02-28 | MIPS FPU dynamic activation, part 1, by Herve Poussineau. | ths |
| 2007-02-27 | Fix mips FPU emulation, 32 bit data types are allowed to use odd registers. | ths |
| 2007-02-18 | Fix sign-extension of VPN field in TLB, by Herve Poussineau. | ths |
| 2007-01-24 | EBase is limited to KSEG0/KSEG1 even on 64bit CPUs. | ths |
| 2007-01-24 | Reworking MIPS interrupt handling, by Aurelien Jarno. | ths |
| 2007-01-23 | Implementing dmfc/dmtc. | ths |
| 2007-01-01 | Fix bad data type. | ths |
| 2006-12-21 | Scrap SIGN_EXTEND32. | ths |
| 2006-12-21 | Preliminiary MIPS64 support, disabled by default due to performance impact. | ths |
| 2006-12-07 | Fix build of MIPS target without FPU support. | ths |
| 2006-12-06 | Add MIPS32R2 instructions, and generally straighten out the instruction | ths |
| 2006-12-06 | Dynamically translate MIPS mtc0 instructions. | ths |
| 2006-12-06 | Dynamically translate MIPS mfc0 instructions. | ths |
| 2006-11-12 | MIPS FPU fixes (Daniel Jacobowitz). | pbrook |
| 2006-10-29 | compilation fix | bellard |
| 2006-10-23 | add support for cvt.s.d and cvt.d.s (Aurelien Jarno) | bellard |
| 2006-06-26 | consistent update of ERL and EXL | bellard |
| 2006-06-14 | MIPS FPU support (Marius Goeger) | bellard |
| 2006-04-23 | MIPS single stepping fix (Dirk Behme) | bellard |
| 2006-04-23 | Fix overflow conditions for MIPS add / subtract (Stefan Weil) | bellard |
| 2005-12-05 | MIPS fixes (Daniel Jacobowitz) | bellard |
