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2010-03-17Large page TLB flushPaul Brook
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-13x86/cpuid: fix indentationAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: Enable all features of real CPUAurelien Jarno
Enable all features of real CPU, unsupported features will be trimmed depending on TCG or KVM capabilities. Move the list of unsupported TCG features near the TCG capabilities masks. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: fix CPUID levelsAndre Przywara
Bump up the xlevel number for qemu32 to allow parsing of the processor name string for this model. Similiarly the 486 processor should have at least the feature bit leaf enabled. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: Always expose 32 and 64-bit CPUsAndre Przywara
Since 64-bit capability is just another CPUID bit we now properly mask, there is no reason anymore to hide the 64-bit capable CPU models from a 32-bit only QEMU. All 64-bit CPUs can be used perfectly in 32-bit legacy mode anyway, so these models also make sense for 32-bit. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: add TCG feature bit trimmingAndre Przywara
In KVM we trim the user provided CPUID bits to match the host CPU's one. Introduce a similar feature to QEMU/TCG. Create a mask of TCG's capabilities and apply it to the user bits. This allows to let the CPU models reflect their native archetypes. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: remove unnecessary kvm_trim functionAndre Przywara
Correct me if I am wrong, but kvm_trim looks like a really bloated implementation of a bitwise AND. So remove this function and replace it with the real stuff(TM). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: add "host" to the list of supported CPU modelsAndre Przywara
Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: add missing CPUID feature flag namesAndre Przywara
Some CPUID feature flags had no string value, so they could not be switched on or off from the command line. Add names for the missing ones mentioned in the current public CPUID specification from both Intel and AMD. Those only mentioned in the Linux kernel source I put as comments. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: moved host_cpuid function and remove prototypeAndre Przywara
the host_cpuid function was located at the end of the file and had a prototype before it's first use. Move it up and remove the prototype. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: fix missing feature set bitsAndre Przywara
This one was accidently removed with commit bb0300dc57c10b3721451b0ff566a03f9276cc77 Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: replace magic number with named constantAndre Przywara
CPUID leaf Fn8000_0001.EDX contains a copy of many Fn0000_0001.EDX bits. Define a name for this mask to improve readability and avoid typos. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13x86/cpuid: move CPUID functions into separate fileAndre Przywara
about half of target-i386/helper.c consist of CPUID related functions. Only one of them is a real TCG helper function. So move the whole CPUID stuff out of this into a separate file to get better maintainable parts. This is only code reordering and should not affect QEMU's functionality. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13target-i386: fix commit c22549204a6edc431e8e4358e61bd56386ff6957TeLeMan
The commit c22549204a6edc431e8e4358e61bd56386ff6957 led movntps & movntdq to be translated incorrectly. Signed-off-by: TeLeMan <geleman@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-12Remove cpu_get_phys_page_debug from userspace emulationPaul Brook
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson
Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-10target-i386: fix SIB decoding with index = 4Aurelien Jarno
A SIB byte with an index of 4 means "no scaled index", even if the scale value is not 0. In 64-bit mode, if REX.X is used, an index of 4 selects %r12. This is correctly handled by the computation of the index variable, which includes the index bits, and also the REX.X prefix: index = ((code >> 3) & 7) | REX_X(s); Thanks to Avi Kivity, Jamie Lokier and Malc for the analysis of the problem and the initial patch. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-06target-i386: Fix long jumps/calls in long mode with REX.W setmalc
Signed-off-by: malc <av1474@comtv.ru> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-06target-i386: fix lddqu SSE instructionAurelien Jarno
This instruction load data from memory to register and not the reverse. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-04KVM: x86: Restrict writeback of VCPU stateJan Kiszka
Do not write nmi_pending, sipi_vector, and mpstate unless we at least go through a reset. And TSC as well as KVM wallclocks should only be written on full sync, otherwise we risk to drop some time on state read-modify-write. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-03-04KVM: Rework VCPU state writeback APIJan Kiszka
This grand cleanup drops all reset and vmsave/load related synchronization points in favor of four(!) generic hooks: - cpu_synchronize_all_states in qemu_savevm_state_complete (initial sync from kernel before vmsave) - cpu_synchronize_all_post_init in qemu_loadvm_state (writeback after vmload) - cpu_synchronize_all_post_init in main after machine init - cpu_synchronize_all_post_reset in qemu_system_reset (writeback after system reset) These writeback points + the existing one of VCPU exec after cpu_synchronize_state map on three levels of writeback: - KVM_PUT_RUNTIME_STATE (during runtime, other VCPUs continue to run) - KVM_PUT_RESET_STATE (on synchronous system reset, all VCPUs stopped) - KVM_PUT_FULL_STATE (on init or vmload, all VCPUs stopped as well) This level is passed to the arch-specific VCPU state writing function that will decide which concrete substates need to be written. That way, no writer of load, save or reset functions that interact with in-kernel KVM states will ever have to worry about synchronization again. That also means that a lot of reasons for races, segfaults and deadlocks are eliminated. cpu_synchronize_state remains untouched, just as Anthony suggested. We continue to need it before reading or writing of VCPU states that are also tracked by in-kernel KVM subsystems. Consequently, this patch removes many cpu_synchronize_state calls that are now redundant, just like remaining explicit register syncs. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-03-04KVM: Rework of guest debug state writingJan Kiszka
So far we synchronized any dirty VCPU state back into the kernel before updating the guest debug state. This was a tribute to a deficite in x86 kernels before 2.6.33. But as this is an arch-dependent issue, it is better handle in the x86 part of KVM and remove the writeback point for generic code. This also avoids overwriting the flushed state later on if user space decides to change some more registers before resuming the guest. We furthermore need to reinject guest exceptions via the appropriate mechanism. That is KVM_SET_GUEST_DEBUG for older kernels and KVM_SET_VCPU_EVENTS for recent ones. Using both mechanisms at the same time will cause state corruptions. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-03-01Move ioport.h out of cpu-all.hPaul Brook
Only include ioport.h where it is actually needed. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-28target-i386: fix crash on x86 32bit linux host with hw breakpoint exceptionsJason Wessel
If you make use of hw breakpoints on a 32bit x86 linux host, qemu will segmentation fault when processing the exception. The problem is that the value of env is stored in $ebp in the op_helper raise_exception() function, and it can have the wrong value when calling it from non generated code. It is possible to work around the problem by restoring the value of env before calling raise_exception() using a new helper function that takes (CPUState *) as one of the arguments. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23Fix OpenBSD linker warningBlue Swirl
helper.o(.text+0x11e0): In function `listflags': /src/qemu/target-i386/helper.c:661: warning: sprintf() is often misused, please use snprintf() Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-23Fix i386-bsd-user buildBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-22Merge remote branch 'qemu-kvm/uq/master' into stagingAnthony Liguori
2010-02-22Add cpu model configuration support..john cooper
This is a reimplementation of prior versions which adds the ability to define cpu models for contemporary processors. The added models are likewise selected via -cpu <name>, and are intended to displace the existing convention of "-cpu qemu64" augmented with a series of feature flags. A primary motivation was determination of a least common denominator within a given processor class to simplify guest migration. It is still possible to modify an arbitrary model via additional feature flags however the goal here was to make doing so unnecessary in typical usage. The other consideration was providing models names reflective of current processors. Both AMD and Intel have reviewed the models in terms of balancing generality of migration vs. excessive feature downgrade relative to released silicon. This version of the patch replaces the prior hard wired definitions with a configuration file approach for new models. Existing models are thus far left as-is but may easily be transitioned to (or may be overridden by) the configuration file representation. Proposed new model definitions are provided here for current AMD and Intel processors. Each model consists of a name used to select it on the command line (-cpu <name>), and a model_id which corresponds to a least common denominator commercial instance of the processor class. A table of names/model_ids may be queried via "-cpu ?model": : x86 Opteron_G3 AMD Opteron 23xx (Gen 3 Class Opteron) x86 Opteron_G2 AMD Opteron 22xx (Gen 2 Class Opteron) x86 Opteron_G1 AMD Opteron 240 (Gen 1 Class Opteron) x86 Nehalem Intel Core i7 9xx (Nehalem Class Core i7) x86 Penryn Intel Core 2 Duo P9xxx (Penryn Class Core 2) x86 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2) : Also added is "-cpu ?dump" which exhaustively outputs all config data for all defined models, and "-cpu ?cpuid" which enumerates all qemu recognized CPUID feature flags. The pseudo cpuid flag 'check' when added to the feature flag list will warn when feature flags (either implicit in a cpu model or explicit on the command line) would have otherwise been quietly unavailable to a guest: # qemu-system-x86_64 ... -cpu Nehalem,check warning: host cpuid 0000_0001 lacks requested flag 'sse4.2|sse4_2' [0x00100000] warning: host cpuid 0000_0001 lacks requested flag 'popcnt' [0x00800000] A similar 'enforce' pseudo flag exists which in addition to the above causes qemu to error exit if requested flags are unavailable. Configuration data for a cpu model resides in the target config file which by default will be installed as: /usr/local/etc/qemu/target-<arch>.conf The format of this file should be self explanatory given the definitions for the above six models and essentially mimics the structure of the static x86_def_t x86_defs. Encoding of cpuid flags names now allows aliases for both the configuration file and the command line which reconciles some Intel/AMD/Linux/Qemu naming differences. This patch was tested relative to qemu.git. Signed-off-by: john cooper <john.cooper@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-02-21kvm: Kill CR3_CACHE feature referencesJes Sorensen
Remove all references to KVM_CR3_CACHE as it was never implemented. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2010-02-19QEMU e820 reservation patchJes Sorensen
Hi, Kevin and I have agreed on the approach for this one now. So here is the latest version of the patch for QEMU, submitting e820 reservation entries via fw_cfg. Cheers, Jes Use qemu-cfg to provide the BIOS with an optional table of e820 entries. Notify the BIOS of the location of the TSS+EPT range to by reserving it via the e820 table. This matches a corresponding patch for Seabios, however older versions of Seabios will default to the hardcoded address range and stay compatible with current QEMU. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-02-08Merge remote branch 'qemu-kvm/uq/master' into staging-tmpAnthony Liguori
2010-02-05remove two dead assignments in target-i386/translate.cPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-03KVM: x86: Fix up misreported CPU featuresJan Kiszka
From qemu-kvm: Kernels before 2.6.30 misreported some essential CPU features via KVM_GET_SUPPORTED_CPUID. Fix them up. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2010-02-03KVM: Request setting of nmi_pending and sipi_vectorJan Kiszka
The final version of VCPU events in 2.6.33 will allow to skip nmi_pending and sipi_vector on KVM_SET_VCPU_EVENTS. For now let's write them unconditionally, which is unproblematic for upstream due to missing SMP support. Future version which enable SMP will write them only on reset. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-01-19kill regs_to_env and env_to_regsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-19remove dead code from target-i386/exec.hPaolo Bonzini
These are unused since edea5f0 (no need to define global registers in cpu-exec.c, 2008-05-10). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-13Add KVM paravirt cpuid leafGleb Natapov
Initialize KVM paravirt cpuid leaf and allow user to control guest visible PV features through -cpu flag. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-13x86: translate.c: remove dead assignmentAmit Shah
clang-analyzer points out a redundant assignment. Signed-off-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-11remove pending exception on vcpu reset.Gleb Natapov
Without this qemu can even start on kvm modules with events support since default value of exception_injected in zero and this is #DE exception. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-11MCE: Fix bug of IA32_MCG_STATUS after system resetHuang Ying
Now, if we inject a fatal MCE into guest OS, for example Linux, Linux will go panic and then reboot. But if we inject another MCE now, system will reset directly instead of go panic firstly, because MCG_STATUS.MCIP is set to 1 and not cleared after reboot. This is does not follow the behavior in real hardware. This patch fixes this via set env->mcg_status to 0 during system reset. Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-03target-i386: Fix "call im" on x86_64 when executing 32-bit codeAurelien Jarno
Similarly to what is done in 32938e127f50a40844a0fb9c5abb8691aeeccf7e for "jmp im", trunc the immediate to 32-bit when not running in 64-bit mode. Reported-by: Kevin O'Connor <kevin@koconnor.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-24Intel CPUs starting from pentium have apicGleb Natapov
Intel CPUs starting from pentium have apic. Lets advertise it. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-18Revert "kvm: x86: Save/restore exception_index"Anthony Liguori
This reverts commit ebbc8a3d8e76d0402f8a08c10c0f32e24715d41d. As suggested by Jan Kiszka, "It was obsoleted by d1793b836f8f123b961c613de1bb1c0c185c84cc and now saves/restores a useless field." Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-18target-i386: Fix evaluation of DR7 registerJan Kiszka
hw_breakpoint_type and hw_breakpoint_len used the wrong index multiplier to extract type and len. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-18kvm: x86: Use separate exception_injected CPUState fieldJan Kiszka
Marcelo correctly remarked that there are usage conflicts between QEMU core code and KVM /wrt exception_index. So spend a separate field and also save/restore it properly. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-13target-i386: Update CPUID feature set for TCGAndre Przywara
The CPUID features QEMU presented to the guest were not up-to-date with QEMU's emulated feature set. Add the missing bits of recent (and not so recent) additions to QEMU's emulation engine. For stability reasons only the user mode usable bits are exposed for now, features like Monitor or CR8LEG are left out. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-12v2: properly save kvm system time msr registersGlauber Costa
Currently, the msrs involved in setting up pvclock are not saved over migration and/or save/restore. This patch puts their value in special fields in our CPUState, and deal with them using vmstate. kvm also has to account for it, by including them in the msr list for the ioctls. This is a backport from qemu-kvm.git [v2: sucessfully build without kerneldir ] Signed-off-by: Glauber Costa <glommer@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-12kvm: x86: Save/restore exception_indexJan Kiszka
As KVM now makes use of exception_index to keep pending exceptions, we have to save&restore this field as well. NOTE: We have to nail the arch-independent exception_index down to a certain bit width for proper vmstate processing, namely to 32 bit. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-07cpuid: Fix multicore setup on IntelAndre Przywara
The multicore CPUID code detects whether the guest is an Intel or an AMD CPU, because the Linux kernel is picky about the CmpLegacy bit. KVM by default passes through the host's vendor, which was not catched by the code. So fork out the vendor determining bits into a separate function to be used from both places and always get the real vendor. This fixes KVM's multicore setup on Intel CPUs. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Reported-by: Dietmar Maurer <dietmar@proxmox.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-07kvm: x86: Fix initial kvm_has_msr_starJan Kiszka
KVM_GET_MSR_INDEX_LIST returns -E2BIG when the provided space is too small for all MSRs. But this is precisely the error we trigger with the initial request in order to obtain that size. Do not fail in that case. This caused a subtle corruption of the guest state as MSR_STAR was not properly saved/restored. The corruption became visible with latest kvm optimizing the MSR updates. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-13 13:37:05 +0000