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path: root/target-arm/helper.c
AgeCommit message (Expand)Author
2014-06-09target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell
2014-06-09target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini
2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson
2014-05-27target-arm: A64: Register VBAR_EL3Edgar E. Iglesias
2014-05-27target-arm: A64: Register VBAR_EL2Edgar E. Iglesias
2014-05-27target-arm: Make vbar_write writeback to any CPREGEdgar E. Iglesias
2014-05-27target-arm: Register EL3 versions of ELR and SPSREdgar E. Iglesias
2014-05-27target-arm: Register EL2 versions of ELR and SPSREdgar E. Iglesias
2014-05-27target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias
2014-05-27target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias
2014-05-27target-arm: Make esr_el1 an arrayEdgar E. Iglesias
2014-05-27target-arm: Make elr_el1 an arrayEdgar E. Iglesias
2014-05-27target-arm: implement CPACR register logic for ARMv7Fabian Aggeler
2014-05-13target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchangedPeter Maydell
2014-05-01target-arm: A64: Fix a typo when declaring TLBI opsEdgar E. Iglesias
2014-05-01target-arm: Make vbar_write 64bit friendly on 32bit hostsEdgar E. Iglesias
2014-05-01target-arm: Implement XScale cache lockdown operations as NOPsPeter Maydell
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell
2014-04-17target-arm: Implement RVBAR registerPeter Maydell
2014-04-17target-arm: Implement AArch64 address translation operationsPeter Maydell
2014-04-17target-arm: Implement auxiliary fault status registersPeter Maydell
2014-04-17target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8Peter Maydell
2014-04-17target-arm: Don't expose wildcard ID register definitions for ARMv8Peter Maydell
2014-04-17target-arm: Implement ISR_EL1 registerPeter Maydell
2014-04-17target-arm: Implement AArch64 view of ACTLRPeter Maydell
2014-04-17target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell
2014-04-17target-arm: Implement AArch64 views of AArch32 ID registersPeter Maydell
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell
2014-04-17target-arm: Move arm_log_exception() into internals.hPeter Maydell
2014-04-17target-arm: Implement AArch64 SPSR_EL1Peter Maydell
2014-04-17target-arm: Implement SP_EL0, SP_EL1Peter Maydell
2014-04-17target-arm: Add AArch64 ELR_EL1 register.Peter Maydell
2014-04-17target-arm: Implement AArch64 views of fault status and data registersRob Herring
2014-04-17target-arm: Use dedicated CPU state fields for ARM946 access bit registersPeter Maydell
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell
2014-04-17target-arm: Don't mention PMU in debug feature registerPeter Maydell
2014-04-17target-arm: Add v8 mmu translation supportRob Herring
2014-04-17target-arm: Provide syndrome information for MMU faultsRob Herring
2014-04-17target-arm: Define exception record for AArch64 exceptionsPeter Maydell
2014-04-17target-arm: Implement AArch64 DAIF system registerPeter Maydell
2014-04-17target-arm: Split out private-to-target functions into internals.hPeter Maydell
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée
2014-03-17target-arm: Add ARM_CP_IO notation to PMCR reginfoPeter Maydell
2014-03-15misc: Fix typos in commentsStefan Weil
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber
2014-03-13cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber
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