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QEMU is a generic and open source machine & userspace emulator and virtualizer
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target-arm
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cpu.h
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2014-05-27
target-arm: Make esr_el1 an array
Edgar E. Iglesias
2014-05-27
target-arm: Make elr_el1 an array
Edgar E. Iglesias
2014-05-27
target-arm: Use a 1:1 mapping between EL and MMU index
Edgar E. Iglesias
2014-04-17
target-arm: Implement CBAR for Cortex-A57
Peter Maydell
2014-04-17
target-arm: Implement AArch64 address translation operations
Peter Maydell
2014-04-17
target-arm: Implement AArch64 view of CONTEXTIDR
Peter Maydell
2014-04-17
target-arm: Implement ARMv8 MVFR registers
Peter Maydell
2014-04-17
target-arm: Implement AArch64 SPSR_EL1
Peter Maydell
2014-04-17
target-arm: Implement SP_EL0, SP_EL1
Peter Maydell
2014-04-17
target-arm: Add AArch64 ELR_EL1 register.
Peter Maydell
2014-04-17
target-arm: Implement AArch64 views of fault status and data registers
Rob Herring
2014-04-17
target-arm: Use dedicated CPU state fields for ARM946 access bit registers
Peter Maydell
2014-04-17
target-arm: A64: Implement DC ZVA
Peter Maydell
2014-04-17
target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1
Peter Maydell
2014-04-17
target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
Peter Maydell
2014-04-17
target-arm: Define exception record for AArch64 exceptions
Peter Maydell
2014-04-17
target-arm: Implement AArch64 DAIF system register
Peter Maydell
2014-04-17
target-arm: Split out private-to-target functions into internals.h
Peter Maydell
2014-03-13
cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook
Andreas Färber
2014-03-13
cpu: Turn cpu_has_work() into a CPUClass hook
Andreas Färber
2014-03-10
target-arm: Implements the ARM PMCCNTR register
Alistair Francis
2014-02-26
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
Will Newton
2014-02-26
target-arm: Add utility function for checking AA32/64 state of an EL
Peter Maydell
2014-02-26
target-arm: Implement AArch64 view of CPACR
Peter Maydell
2014-02-26
target-arm: Store AIF bits in env->pstate for AArch32
Peter Maydell
2014-02-26
target-arm: Get MMU index information correct for A64 code
Peter Maydell
2014-02-26
target-arm: Implement AArch64 dummy breakpoint and watchpoint registers
Peter Maydell
2014-02-26
target-arm: Implement AArch64 generic timers
Peter Maydell
2014-02-26
target-arm: Implement AArch64 TTBR*
Peter Maydell
2014-02-26
target-arm: Implement AArch64 VBAR_EL1
Peter Maydell
2014-02-26
target-arm: Implement AArch64 TCR_EL1
Peter Maydell
2014-02-26
target-arm: Implement AArch64 SCTLR_EL1
Peter Maydell
2014-02-26
target-arm: Implement AArch64 memory attribute registers
Peter Maydell
2014-02-26
target-arm: Implement AArch64 CurrentEL sysreg
Peter Maydell
2014-02-26
target-arm: A64: Make cache ID registers visible to AArch64
Peter Maydell
2014-02-26
target-arm: Fix raw read and write functions on AArch64 registers
Peter Maydell
2014-02-20
target-arm: Drop success/fail return from cpreg read and write functions
Peter Maydell
2014-02-20
target-arm: Split cpreg access checks out from read/write functions
Peter Maydell
2014-02-20
target-arm: Remove unused ARMCPUState sr substruct
Peter Maydell
2014-02-20
target-arm: Define names for SCTLR bits
Peter Maydell
2014-01-31
target-arm: Move arm_rmode_to_sf to a shared location.
Will Newton
2014-01-12
arm: fix compile on bigendian host
Alexey Kardashevskiy
2014-01-08
target-arm: Give the FPSCR rounding modes names
Alexander Graf
2014-01-08
target-arm: Widen exclusive-access support struct fields to 64 bits
Peter Maydell
2014-01-07
target-arm: Widen thread-local register state fields to 64 bits
Peter Maydell
2014-01-07
target-arm: A64: Implement minimal set of EL0-visible sysregs
Peter Maydell
2014-01-07
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
Peter Maydell
2014-01-04
target-arm: Update generic cpreg code for AArch64
Peter Maydell
2013-12-17
target-arm: A64: provide functions for accessing FPCR and FPSR
Peter Maydell
2013-12-17
target-arm: Clean up handling of AArch64 PSTATE
Peter Maydell
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