slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2020-06-19	hw/riscv: sifive_u: Add a dummy DDR memory controller device	Bin Meng
2020-06-19	hw/riscv: sifive_u: Support different boot source per MSEL pin state	Bin Meng
2020-06-19	hw/riscv: sifive_u: Add a new property msel for MSEL pin state	Bin Meng
2020-06-19	hw/riscv: sifive_u: Hook a GPIO controller	Bin Meng
2020-06-19	hw/riscv: sifive_gpio: Add a new 'ngpio' property	Bin Meng
2020-06-19	hw/riscv: sifive_gpio: Clean up the codes	Bin Meng
2020-06-19	riscv/opentitan: Connect the UART device	Alistair Francis
2020-06-19	riscv/opentitan: Connect the PLIC device	Alistair Francis
2020-06-19	sifive_e: Support the revB machine	Alistair Francis
2020-06-15	riscv: Fix type of SiFive[EU]SocState, member parent_obj	Markus Armbruster
2020-06-03	riscv: Initial commit of OpenTitan machine	Alistair Francis
2020-06-03	riscv/boot: Add a missing header include	Alistair Francis
2020-06-03	riscv: sifive_e: Manually define the machine	Alistair Francis
2020-06-03	hw/riscv: spike: Remove deprecated ISA specific machines	Alistair Francis
2020-04-29	hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()	Anup Patel
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u machine	Bin Meng
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u SoC	Alistair Francis
2020-02-27	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	Anup Patel
2020-02-10	riscv: virt: Use Goldfish RTC device	Anup Patel
2019-11-25	hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()	Zhuang, Siwei (Data61, Kensington NSW)
2019-10-28	riscv/virt: Add the PFlash CFI01 device	Alistair Francis
2019-10-28	riscv/virt: Manually define the machine	Alistair Francis
2019-10-28	riscv/sifive_u: Add the start-in-flash property	Alistair Francis
2019-10-28	riscv/sifive_u: Manually define the machine	Alistair Francis
2019-10-28	riscv/sifive_u: Add QSPI memory region	Alistair Francis
2019-10-28	riscv/sifive_u: Add L2-LIM cache memory	Alistair Francis
2019-10-28	riscv: hw: Drop "clock-frequency" property of cpu nodes	Bin Meng
2019-09-17	riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet	Bin Meng
2019-09-17	riscv: sifive_u: Fix broken GEM support	Bin Meng
2019-09-17	riscv: sifive_u: Instantiate OTP memory with a serial number	Bin Meng
2019-09-17	riscv: sifive: Implement a model for SiFive FU540 OTP	Bin Meng
2019-09-17	riscv: sifive_u: Update UART base addresses and IRQs	Bin Meng
2019-09-17	riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes	Bin Meng
2019-09-17	riscv: sifive_u: Add PRCI block to the SoC	Bin Meng
2019-09-17	riscv: sifive_u: Generate hfclk and rtcclk nodes	Bin Meng
2019-09-17	riscv: sifive: Implement PRCI model for FU540	Bin Meng
2019-09-17	riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC	Bin Meng
2019-09-17	riscv: sifive_u: Set the minimum number of cpus to 2	Bin Meng
2019-09-17	riscv: hart: Add a "hartid-base" property to RISC-V hart array	Bin Meng
2019-09-17	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	Bin Meng
2019-09-17	riscv: sifive_e: prci: Update the PRCI register block size	Bin Meng
2019-09-17	riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}	Bin Meng
2019-09-17	riscv: sifive_test: Add reset functionality	Bin Meng
2019-09-17	riscv: Add a helper routine for finding firmware	Bin Meng
2019-09-17	riscv: plic: Remove unused interrupt functions	Alistair Francis
2019-08-16	Clean up inclusion of sysemu/sysemu.h	Markus Armbruster
2019-08-16	Include hw/hw.h exactly where needed	Markus Armbruster
2019-08-16	include: Make headers more self-contained	Markus Armbruster
2019-07-18	hw/riscv: Load OpenSBI as the default firmware	Alistair Francis
2019-06-27	hw/riscv: Add support for loading a firmware	Alistair Francis