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2024-10-15hw/misc: Create STM32L4x5 SYSCFG clockInès Varhol
This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the corresponding clock from STM32L4x5 RCC. Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20241003081105.40836-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-15hw/misc/stm32_rcc: Implement RCC device for STM32F4 SoCsRomán Cárdenas Rodríguez
Generic RCC class for STM32 devices. It can be used for most of the STM32 chips. Note that it only implements enable and reset capabilities. Signed-off-by: Roman Cardenas Rodriguez <rcardenas.rod@gmail.com> [PMM: tweaked commit message, added MAINTAINERS lines] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-01hw/misc: Remove cbusPeter Maydell
The devices in hw/misc/cbus.c were used only by the now-removed nseries machine types, so they can be removed. As this is the last use of the CONFIG_NSERIES define we can remove that from KConfig now. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240903160751.4100218-27-peter.maydell@linaro.org
2024-09-05hw/misc/xlnx-versal-trng: Call register_finalize_blockPeter Maydell
The TYPE_XLNX_VERSAL_TRNG device creates a register block with register_init_block32() in its instance_init method; we must therefore destroy it in our instance_finalize method to avoid a leak in the QOM introspection "init-inspect-finalize" lifecycle: Direct leak of 304 byte(s) in 1 object(s) allocated from: #0 0x55842ec799d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294e9d8) (BuildId: 47496e53f3e779f1c7e9b82cbea07407152b498b) #1 0x7fe793c75c50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x55842f0aec5d in register_init_block hw/core/register.c:248:34 #3 0x55842f0af6be in register_init_block32 hw/core/register.c:299:12 #4 0x55842f801588 in trng_init hw/misc/xlnx-versal-trng.c:614:9 #5 0x558431c411a1 in object_init_with_type qom/object.c:420:9 #6 0x558431c2847b in object_initialize_with_type qom/object.c:562:5 #7 0x558431c29d1d in object_new_with_type qom/object.c:782:5 #8 0x558431c29df1 in object_new qom/object.c:797:12 #9 0x558432427c1d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240822162127.705879-6-peter.maydell@linaro.org
2024-07-21aspeed/scu: Add boot-from-eMMC HW strapping bit for AST2600 SoCCédric Le Goater
Bit SCU500[2] of the AST2600 controls the boot device of the SoC. Future changes will configure this bit to boot from eMMC disk images specially built for this purpose. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-07-11hw/misc: In STM32L4x5 EXTI, consolidate 2 constantsInès Varhol
Up until now, the EXTI implementation had 16 inbound GPIOs connected to the 16 outbound GPIOs of STM32L4x5 SYSCFG. The EXTI actually handles 40 lines (namely 5 from STM32L4x5 USART devices which are already implemented in QEMU). In order to connect USART devices to EXTI, this commit consolidates constants `EXTI_NUM_INTERRUPT_OUT_LINES` (40) and `EXTI_NUM_GPIO_EVENT_IN_LINES` (16) into `EXTI_NUM_LINES` (40). Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240707085927.122867-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-03Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Richard Henderson
into staging virtio: features,fixes A bunch of improvements: - vhost dirty log is now only scanned once, not once per device - virtio and vhost now support VIRTIO_F_NOTIFICATION_DATA - cxl gained DCD emulation support - pvpanic gained shutdown support - beginning of patchset for Generic Port Affinity Structure - s3 support - friendlier error messages when boot fails on some illegal configs - for vhost-user, VHOST_USER_SET_LOG_BASE is now only sent once - part of vhost-user support for any POSIX system - not yet enabled due to qtest failures - sr-iov VF setup code has been reworked significantly - new tests, particularly for risc-v ACPI - bugfixes Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmaF068PHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRp+DMIAMC//mBXIZlPprfhb5cuZklxYi31Acgu5TUr # njqjCkN+mFhXXZuc3B67xmrQ066IEPtsbzCjSnzuU41YK4tjvO1g+LgYJBv41G16 # va2k8vFM5pdvRA+UC9li1CCIPxiEcszxOdzZemj3szWLVLLUmwsc5OZLWWeFA5m8 # vXrrT9miODUz3z8/Xn/TVpxnmD6glKYIRK/IJRzzC4Qqqwb5H3ji/BJV27cDUtdC # w6ns5RYIj5j4uAiG8wQNDggA1bMsTxFxThRDUwxlxaIwAcexrf1oRnxGRePA7PVG # BXrt5yodrZYR2sR6svmOOIF3wPMUDKdlAItTcEgYyxaVo5rAdpc= # =p9h4 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 03 Jul 2024 03:41:51 PM PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (85 commits) hw/pci: Replace -1 with UINT32_MAX for romsize pcie_sriov: Register VFs after migration pcie_sriov: Remove num_vfs from PCIESriovPF pcie_sriov: Release VFs failed to realize pcie_sriov: Reuse SR-IOV VF device instances pcie_sriov: Ensure VF function number does not overflow pcie_sriov: Do not manually unrealize hw/ppc/spapr_pci: Do not reject VFs created after a PF hw/ppc/spapr_pci: Do not create DT for disabled PCI device hw/pci: Rename has_power to enabled virtio-iommu: Clear IOMMUDevice when VFIO device is unplugged virtio: remove virtio_tswap16s() call in vring_packed_event_read() hw/cxl/events: Mark cxl-add-dynamic-capacity and cxl-release-dynamic-capcity unstable hw/cxl/events: Improve QMP interfaces and documentation for add/release dynamic capacity. tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs meson.build: Add RISC-V to the edk2-target list tests/data/acpi/virt: Move ARM64 ACPI tables under aarch64/${machine} path tests/data/acpi: Move x86 ACPI tables under x86/${machine} path tests/qtest/bios-tables-test.c: Set "arch" for x86 tests ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-02Merge tag 'hw-misc-20240702' of https://github.com/philmd/qemu into stagingRichard Henderson
Misc HW patches queue - Prevent NULL deref in sPAPR network model (Oleg) - Automatic deprecation of versioned machine types (Daniel) - Correct 'dump-guest-core' property name in hint (Akihiko) - Prevent IRQ leak in MacIO IDE model (Mark) - Remove dead #ifdef'ry related to unsupported macOS 12.0 (Akihiko) - Remove "hw/hw.h" where unnecessary (Thomas) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmaDiSQACgkQ4+MsLN6t # wN4jmBAA2kxwFAGbKvokANDAZBwWmJdnuIPcqS+jdo/wCuQXOo1ROADd3NFlgQWx # z1xOv/LiAmQiUeeiP+nlA8gWCdW93PErU07og1p1+N2D1sBO6oG5QDlT/tTFuEGd # IL21jG2xWkEemd3PSN2pHKrytpS0e4S0cNZIKgTUTKdv+Mb2ZEiQi7K4zUTjcmjz # nlsSjTXdyKBmoiqNGhITWfbR2IUWjtCpzUO44ceqXd5HDpvfGhpKI7Uwun1W2xNU # yw1XrAFd64Qhd/lvc28G1DLfDdtRIoaRGxgLzQbU6621s0o50Ecs6TNHseuUAKvd # tQhOtM8IEuZ6jVw8nswCPIcJyjbeY29kjI4WmD2weF1fZbDey6Emlrf+dkJUIuCb # TximyTXw3rb1nREUVsEQLF69BKjTjE5+ETaplcTWGHCoH2+uA/5MqygalTH1Ub9W # TwVWSUwpNvIJ3RTsT20YVowkill8piF+ECldTKzJuWjqDviiJDoMm5EFdkkcUB20 # nMyhGoiXtiQ4NYU0/B6HbHOXZkqLbhWcx9G281xJ+RRwjUyVxXD3zHGR9AoOp9ls # EAo/2URJtGN95LJmzCtaD+oo0wRZ5+7lmnqHPPXkYUdwFm4bhe3dP4NggIrS0cXn # 19wvBqQuPwywxIbFEu6327YtfPRcImWIlFthWnm9lUyDmbOqDKw= # =fLCx # -----END PGP SIGNATURE----- # gpg: Signature made Mon 01 Jul 2024 09:59:16 PM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'hw-misc-20240702' of https://github.com/philmd/qemu: (22 commits) Remove inclusion of hw/hw.h from files that don't need it net/vmnet: Drop ifdef for macOS versions older than 12.0 block/file-posix: Drop ifdef for macOS versions older than 12.0 audio: Drop ifdef for macOS versions older than 12.0 hvf: Drop ifdef for macOS versions older than 12.0 hw/ide/macio: switch from using qemu_allocate_irq() to qdev input GPIOs system/physmem: Fix reference to dump-guest-core docs: document special exception for machine type deprecation & removal hw/i386: remove obsolete manual deprecation reason string of i440fx machines hw/ppc: remove obsolete manual deprecation reason string of spapr machines hw: skip registration of outdated versioned machine types hw: set deprecation info for all versioned machine types include/hw: temporarily disable deletion of versioned machine types include/hw: add macros for deprecation & removal of versioned machines hw/i386: convert 'q35' machine definitions to use new macros hw/i386: convert 'i440fx' machine definitions to use new macros hw/m68k: convert 'virt' machine definitions to use new macros hw/ppc: convert 'spapr' machine definitions to use new macros hw/s390x: convert 'ccw' machine definitions to use new macros hw/arm: convert 'virt' machine definitions to use new macros ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-02Remove inclusion of hw/hw.h from files that don't need itThomas Huth
hw/hw.h only contains the prototype of hw_error() nowadays, so files that don't use this function don't need to include this header. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240701132649.58345-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-07-02hw/ide/macio: switch from using qemu_allocate_irq() to qdev input GPIOsMark Cave-Ayland
This prevents the IRQs from being leaked when the macio IDE device is used. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240628160334.653168-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-07-01hw/misc/pvpanic: add support for normal shutdownsThomas Weißschuh
Shutdown requests are normally hardware dependent. By extending pvpanic to also handle shutdown requests, guests can submit such requests with an easily implementable and cross-platform mechanism. Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Message-Id: <20240527-pvpanic-shutdown-v8-5-5a28ec02558b@t-8ch.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-07-01hw/misc/pvpanic: centralize definition of supported eventsThomas Weißschuh
The different components of pvpanic duplicate the list of supported events. Move it to the shared header file to minimize changes when new events are added. MST: tweak: keep header included in pvpanic.c to avoid header dependency, rebase. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Message-Id: <20240527-pvpanic-shutdown-v8-3-5a28ec02558b@t-8ch.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-07-01hw/misc: In STM32L4x5 EXTI, correct configurable interruptsInès Varhol
The implementation of configurable interrupts (interrupts supporting edge selection) was incorrectly expecting alternating input levels : this commits adds a new status field `irq_levels` to actually detect edges. Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240629110800.539969-2-ines.varhol@telecom-paris.fr Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01hw/misc: Implement mailbox properties for customer OTP and device specific ↵Rayhan Faizel
private keys Four mailbox properties are implemented as follows: 1. Customer OTP: GET_CUSTOMER_OTP and SET_CUSTOMER_OTP 2. Device-specific private key: GET_PRIVATE_KEY and SET_PRIVATE_KEY. The customer OTP is located in the rows 36-43. The device-specific private key is located in the rows 56-63. The customer OTP can be locked with the magic numbers 0xffffffff 0xaffe0000 when running the SET_CUSTOMER_OTP mailbox command. Bit 6 of row 32 indicates this lock, which is undocumented. The lock also applies to the device-specific private key. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-16aspeed/scu: Add AST2700 supportJamin Lin
AST2700 have two SCU controllers which are SCU and SCUIO. Both SCU and SCUIO registers are not compatible previous SOCs , introduces new registers and adds ast2700 scu, sucio class init handler. The pclk divider selection of SCUIO is defined in SCUIO280[20:18] and the pclk divider selection of SCU is defined in SCU280[25:23]. Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function and trace-event for AST2700 SCU and SCUIO. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [clg: Fixed spelling : Unhandeled -> Unhandled ]
2024-06-16aspeed/sdmc: Add AST2700 supportJamin Lin
The SDRAM memory controller(DRAMC) controls the access to external DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY. The DRAM memory controller of AST2700 is not backward compatible to previous chips such AST2600, AST2500 and AST2400. Max memory is now 8GiB on the AST2700. Introduce new aspeed_2700_sdmc and class with read/write operation and reset handlers. Define DRAMC necessary protected registers and unprotected registers for AST2700 and increase the register set to 0x1000. Add unlocked property to change controller protected status. Incrementing the version of vmstate to 2. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2024-06-16aspeed/sli: Add AST2700 supportJamin Lin
AST2700 SLI engine is designed to accelerate the throughput between cross-die connections. It have CPU_SLI at CPU die and IO_SLI at IO die. Introduce dummy AST2700 SLI and SLIIO models. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2024-03-25misc/pca955*: Move models under hw/gpioCédric Le Goater
The PCA9552 and PCA9554 devices are both I2C GPIO controllers and the PCA9552 also can drive LEDs. Do all the necessary adjustments to move the models under hw/gpio. Cc: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Message-ID: <20240325134833.1484265-1-clg@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-03-07hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoCInès Varhol
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexersArnaud Minier
Instantiate the whole clock tree and using the Clock multiplexers and the PLLs defined in the previous commits. This allows to statically define the clock tree and easily follow the clock signal from one end to another. Also handle three-phase reset now that we have defined a known base state for every object. (Reset handling based on hw/misc/zynq_sclr.c) Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240303140643.81957-5-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/misc/stm32l4x5_rcc: Add an internal PLL Clock objectArnaud Minier
This object represents the PLLs and their channels. The PLLs allow for a more fine-grained control of the clocks frequency. The migration handling is based on hw/misc/zynq_sclr.c. Three phase reset will be handled in a later commit. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240303140643.81957-4-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/misc/stm32l4x5_rcc: Add an internal clock multiplexer objectArnaud Minier
This object is used to represent every multiplexer in the clock tree as well as every clock output, every presecaler, frequency multiplier, etc. This allows to use a generic approach for every component of the clock tree (except the PLLs). The migration handling is based on hw/misc/zynq_sclr.c. Three phase reset will be handled in a later commit. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240303140643.81957-3-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/misc/stm32l4x5_rcc: Implement STM32L4x5_RCC skeletonArnaud Minier
Add the necessary files to add a simple RCC implementation with just reads from and writes to registers. Also instantiate the RCC in the STM32L4x5_SoC. It is needed for accurate emulation of all the SoC clocks and timers. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240303140643.81957-2-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/ide: Remove last two uses of ide/internal.h outside of hw/ide/BALATON Zoltan
Remove last two includes of hw/ide/intarnal.h outside of hw/ide and replace them with newly added public header to allow moving internal.h into hw/ide to really stop exposing it. Fixes: a11f439a0e (hw/ide: Stop exposing internal.h to non-IDE files) Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240223142633.933694E6004@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-23misc: Add a pca9554 GPIO device modelGlenn Miles
Specs are available here: https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf This is a simple model supporting the basic registers for GPIO mode. The device also supports an interrupt output line but the model does not yet support this. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23misc/pca9552: Let external devices set pca9552 inputsGlenn Miles
Allow external devices to drive pca9552 input pins by adding input GPIO's to the model. This allows a device to connect its output GPIO's to the pca9552 input GPIO's. In order for an external device to set the state of a pca9552 pin, the pin must first be configured for high impedance (LED is off). If the pca9552 pin is configured to drive the pin low (LED is on), then external input will be ignored. Here is a table describing the logical state of a pca9552 pin given the state being driven by the pca9552 and an external device: PCA9552 Configured State | Hi-Z | Low | ------+------+-----+ External Hi-Z | Hi | Low | Device ------+------+-----+ State Low | Low | Low | ------+------+-----+ Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-16Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu into stagingPeter Maydell
Misc HW patch queue - Remove unused MIPS SAAR* registers (Phil) - Remove warning when testing the TC58128 NAND EEPROM (Peter) - KConfig cleanups around ISA SuperI/O and MIPS (Paolo) - QDev API uses sanitization (Philippe) - Split AHCI model as PCI / SysBus (Philippe) - Add SMP support to SPARC Leon3 board (Clément) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmXOUD4ACgkQ4+MsLN6t # wN6gWRAAjf+6Z9VUvvHqZoaSJW49k+GRUelTI2tyN+eGfetAx9dk8aIbpbV1X12d # pc56jsSi6ICT7baCegtxHszhYJr2e9A2QLCAOJt+Oz87kEGes3ONVVKAk7pwjKxt # m8pmU3uXWgFvU6PoFBhGBa6LiZBulgLNXBUwzmEhc9PpPkR49ULdDp/qxtWvxOV5 # xYBktFlkiT+AvHq3QWCnDIaw+pH5ghEq9BI4xFOvvvqSqdHEqsGAaiKPa9Po0Gfz # Ap9qsm4FxKxhGoeQWtAIP8TvN3pFFSXMysziP6Xt1rffKsvF9ioghGKRM6BgQfqD # ZetjcFbcf7dQu3zZVy8ljYcymMxfZcWWVVq4CMC68lPQE97hz1CT3PJjgd77dKfi # z60uRkOGaiPW5iIGT9+vdQxZ5K3HivKyjuHOdV8V4HnWO3oqgfDtNHn5RKed0qUg # g1FoWriJGsDixdx1vd0EoH2/oTxy4HIsFv7a1OjiZyBLjO+EeEZ3+H9pqUHqBxva # +Dv70z9F1sv5dzcUXH+oCgTbnKlJ90Q+e3vj0wGdlBncVsgIwbtgqYelhUEl+xJX # Mu6KNUo5ANVP38ZKG0GSMCZHfcUjc5s+5rG55NbTN0HiF56a6D2KlQAuXdUsGE1J # 7i4cwipJmfxzbdPDlSb3kBxm5pFexEk6nROF9kTHQj3ZBMMvIls= # =nOX+ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 15 Feb 2024 17:56:14 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20240215' of https://github.com/philmd/qemu: (56 commits) hw/ide/ich9: Use AHCIPCIState typedef hw/ide/ahci: Move SysBus definitions to 'ahci-sysbus.h' hw/ide/ahci: Remove SysbusAHCIState::num_ports field hw/ide/ahci: Do not pass 'ports' argument to ahci_realize() hw/ide/ahci: Convert AHCIState::ports to unsigned hw/ide/ahci: Pass AHCI context to ahci_ide_create_devs() hw/ide/ahci: Inline ahci_get_num_ports() hw/ide/ahci: Rename AHCI PCI function as 'pdev' hw/ide/ahci: Expose AHCIPCIState structure hw/i386/q35: Use DEVICE() cast macro with PCIDevice object hw/i386/q35: Simplify pc_q35_init() since PCI is always enabled MAINTAINERS: Add myself as reviewer for TCG Plugins MAINTAINERS: replace Fabien by myself as Leon3 maintainer hw/sparc/leon3: Initialize GPIO before realizing CPU devices hw/sparc/leon3: Pass DeviceState opaque argument to leon3_start_cpu() hw/sparc/leon3: Pass DeviceState opaque argument to leon3_set_pil_in() hw/sparc/leon3: check cpu_id in the tiny bootloader hw/sparc/leon3: implement multiprocessor hw/sparc/leon3: remove SP initialization target/sparc: implement asr17 feature for smp ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-15hw/misc/mips_itu: Remove MIPSITUState::saar fieldPhilippe Mathieu-Daudé
This field is not set. Remove it along with the dead code it was guarding. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240209090513.9401-7-philmd@linaro.org>
2024-02-15hw/misc/mips_itu: Remove MIPSITUState::cpu0 fieldPhilippe Mathieu-Daudé
Since previous commit the MIPSITUState::cpu0 field is not used anymore. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240209090513.9401-6-philmd@linaro.org>
2024-02-15hw/misc/mips: Reduce itc_reconfigure() scopePhilippe Mathieu-Daudé
Previous commit removed the MT*C0(SAAR) helpers which were the only calls to itc_reconfigure() out of hw/, we can reduce its scope and declare it statically. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240209090513.9401-3-philmd@linaro.org>
2024-02-15hw/misc/mps2-scc: Make changes needed for AN536 FPGA imagePeter Maydell
The MPS2 SCC device is broadly the same for all FPGA images, but has minor differences in the behaviour of the CFG registers depending on the image. In many cases we don't really care about the functionality controlled by these registers and a reads-as-written or similar behaviour is sufficient for the moment. For the AN536 the required behaviour is: * A_CFG0 has CPU reset and halt bits - implement as reads-as-written for the moment * A_CFG1 has flash or ATCM address 0 remap handling - QEMU doesn't model this; implement as reads-as-written * A_CFG2 has QSPI select (like AN524) - implemented (no behaviour, as with AN524) * A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits" - QEMU doesn't care about these, so use the existing RAZ behaviour for convenience * A_CFG4 is board rev (like all other images) - no change needed * A_CFG5 is ACLK frq in hz (like AN524) - implemented as reads-as-written, as for other boards * A_CFG6 is core 0 vector table base address - implemented as reads-as-written for the moment * A_CFG7 is core 1 vector table base address - implemented as reads-as-written for the moment Make the changes necessary for this; leave TODO comments where appropriate to indicate where we might want to come back and implement things like CPU reset. The other aspects of the device specific to this FPGA image (like the values of the board ID and similar registers) will be set via the device's qdev properties. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
2024-02-11lasi: Add reset I/O ports for LASI audio and FDCHelge Deller
Linux writes zeroes at bootup into the default ports for LASI audio and LASI floppy controller to reset those devices. Allow writing to those registers to avoid HPMCs. Signed-off-by: Helge Deller <deller@gmx.de>
2024-01-26hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h'Philippe Mathieu-Daudé
"target/arm/cpu.h" is target specific, any file including it becomes target specific too, thus this is the same for any file including "hw/misc/xlnx-versal-crl.h". "hw/misc/xlnx-versal-crl.h" doesn't require any target specific definition however, only the target-agnostic QOM definitions from "target/arm/cpu-qom.h". Include the latter header to avoid tainting unnecessary objects as target-specific. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-14-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-15hw/misc: Implement STM32L4x5 SYSCFGInès Varhol
Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240109194438.70934-2-ines.varhol@telecom-paris.fr Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-15hw/misc: Implement STM32L4x5 EXTIInès Varhol
Although very similar to the STM32F4xx EXTI, STM32L4x5 EXTI generates more than 32 event/interrupt requests and thus uses more registers than STM32F4xx EXTI which generates 23 event/interrupt requests. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240109160658.311932-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-12-20Merge tag 'pull-request-2023-12-20' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi
staging * Add compat machines for QEMU 9.0 * Some header clean-ups by Philippe * Restrict type names to alphanumerical range (and a few special characters) * Fix analyze-migration.py script on s390x * Clean up and improve some tests * Document handling of commas in CLI options parameters # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmWCtYsRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWLnw//cNJrxG0V+j0iakX+C7HRumVrLBDI4KYY # Cp2Hx92SyeQ0Kk8DJS6JueTV0SLjMsV77APu2YPH7ELmPlk+CB9gqmV7xVoYNvsm # QbRPlIjFw8MHLekadc2A+C+pn48tWACoOdBEDIfazKrxybnf0B57RC/fIfMKHjbs # 2ALCoFbbgphs7yWuzTHK8ayKaGMhUVkWfzHQwpnq899olHyZBhkl951uKJA6VmLx # KvggePkpszLjmmXA8MH1hDCcizki31cB0ZKTbQFCyE42s2S3Hvg0GueU90O7Y1cj # lS5tPVQxyEhUYMLL+/hudlf2OYqVn2BalB7ieUQIy6rG8yoc9zxfIKQi0ccl+2oA # s8HRq5S0bSjtilQogU1LQL/Gk6W1/N9MmnhKvCGB+BTK5KX7s4EQk02y9gGZm/8s # pMErMyaXTG4dLiTAK42VgMVDqCYvzBmE+Gj91OmoUR7fb+VMrsWxeBFxMPDn+VtL # TMJegIFsjw2QCSitcU4v+nP0qtKgXGbuZtrGXKabrxH5PmeQFJDSM7TwpTK4qvjK # QMIQKBbz8BfJnUzN8qAaaJEpp1T5tcMJClKtfcgxq/+VyaSaHLmD0cljqBC+g+y7 # FTo+fa7oYx44sAlqapdEXBSGn4T+J26iuCef13CCCiPfYBv/tk3b2E0AWHj4y58I # +VpInjUaPBQ= # =TA1/ # -----END PGP SIGNATURE----- # gpg: Signature made Wed 20 Dec 2023 04:36:11 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-12-20' of https://gitlab.com/thuth/qemu: tests/unit/test-qmp-event: Replace fixture by global variables tests/unit/test-qmp-event: Simplify event emission check tests/unit/test-qmp-event: Drop superfluous mutex tests/qtest/npcm7xx_pwm-test: Only do full testing in slow mode qemu-options: Clarify handling of commas in options parameters tests/qtest/migration-test: Fix analyze-migration.py for s390x qom/object: Limit type names to alphanumerical and some few special characters tests/unit/test-io-task: Rename "qemu:dummy" to avoid colon in the name memory: Remove "qemu:" prefix from the "qemu:ram-discard-manager" type name hw: Replace anti-social QOM type names (again) docs/system/arm: Fix for rename of type "xlnx.bbram-ctrl" target: Restrict 'sysemu/reset.h' to system emulation hw/s390x/ipl: Remove unused 'exec/exec-all.h' included header hw/misc/mips_itu: Remove unnecessary 'exec/exec-all.h' header hw/ppc/spapr_hcall: Remove unused 'exec/exec-all.h' included header system/qtest: Restrict QTest API to system emulation system/qtest: Include missing 'hw/core/cpu.h' header MAINTAINERS: Add some more vmware-related files to the corresponding section hw: Add compat machines for 9.0 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-12-20hw: Replace anti-social QOM type names (again)Markus Armbruster
QOM type names containing ',' result in awful UI. We got rid of them in v6.0.0 (commit e178113ff64 hw: Replace anti-social QOM type names). A few have crept back since: xlnx,cframe-reg xlnx,efuse xlnx,pmc-efuse-cache xlnx,versal-cfu-apb xlnx,versal-cfu-fdro xlnx,versal-cfu-sfr xlnx,versal-crl xlnx,versal-efuse xlnx,zynqmp-efuse These are all device types. They can't be plugged with -device / device_add, except for "xlnx,efuse" (I'm not sure that one is intentional). They *can* be used with -device / device_add to request help. Usability is poor, though: you have to double the comma, like this: $ qemu-system-aarch64 -device xlnx,,pmc-efuse-cache,help They can also be used with -global, where you must *not* double the comma: $ qemu-system-aarch64 -global xlnx,efuse.drive-index=2 Trap for the unwary. "xlnx,efuse", "xlnx,versal-efuse", "xlnx,pmc-efuse-cache", "xlnx-zynqmp-efuse" are from v6.2.0, "xlnx,versal-crl" is from v7.1.0, and the remainder are new. Rename them all to "xlnx-FOO", like commit e178113ff64 did. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-ID: <20231117114457.177308-3-thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-12-19fsl-imx: add simple RTC emulation for i.MX6 and i.MX7 boardsNikita Ostrenkov
Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com> Message-id: 20231216133408.2884-1-n.ostrenkov@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-27hw/misc, hw/ssi: Fix some URLs for AMD / Xilinx modelsFrederic Konrad
It seems that the url changed a bit, and it triggers an error. Fix the URLs so the documentation can be reached again. Signed-off-by: Frederic Konrad <fkonrad@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20231124143505.1493184-3-fkonrad@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-02hw/misc: Introduce AMD/Xilix Versal TRNG deviceTong Ho
This adds a non-cryptographic grade implementation of the model for the True Random Number Generator (TRNG) component in AMD/Xilinx Versal device family. This implements all 3 modes defined by the actual hardware specs, all of which selectable by guest software at will at anytime: 1) PRNG mode, in which the generated sequence is required to be reproducible after reseeded by the same 384-bit value as supplied by guest software. 2) Test mode, in which the generated sequence is required to be reproducible ater reseeded by the same 128-bit test seed supplied by guest software. 3) TRNG mode, in which non-reproducible sequence is generated based on periodic reseed by a suitable entropy source. This model is only intended for non-real world testing of guest software, where cryptographically strong PRNG or TRNG is not needed. This model supports versions 1 & 2 of the device, with default to be version 2; the 'hw-version' uint32 property can be set to 0x0100 to override the default. Other implemented properties: - 'forced-prng', uint64 When set to non-zero, mode 3's entropy source is implemented as a deterministic sequence based on the given value and other deterministic parameters. This option allows the emulation to test guest software using mode 3 and to reproduce data-dependent defects. - 'fips-fault-events', uint32, bit-mask bit 3: Triggers the SP800-90B entropy health test fault irq bit 1: Triggers the FIPS 140-2 continuous test fault irq Signed-off-by: Tong Ho <tong.ho@amd.com> Message-id: 20231031184611.3029156-2-tong.ho@amd.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-20Merge tag 'hw-misc-20231019' of https://github.com/philmd/qemu into stagingStefan Hajnoczi
Misc hardware patch queue - MAINTAINERS updates (Zoltan, Thomas) - Fix cutils::get_relocated_path on Windows host (Akihiko) - Housekeeping in Memory APIs (Marc-André) - SDHCI fix for SDMA transfer (Lu, Jianxian) - Various QOM/QDev/SysBus cleanups (Philippe) - Constify QemuInputHandler structure (Philippe) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmUxnKAACgkQ4+MsLN6t # wN6UPw//abFZgckpxDYow4UfMu7esvkhICBvXjqDEdX2U/PBYmef049T5RVW8oDm # NWnxRA9XydzTeToH56tU2tjXbjWKF5LcJVwrCNl6XFRdLYaR3hzejm96hX99C89J # PB/2ineeAwidBoFfgjkvz0FLRr1ePaN74YXedPSHzywG+0dAOvpNUubbsggn3i5k # 1wTlgfDvL6iz8NMEOSBp6cv5D4Ix0WshkqlCac0gQ74lYSM1tk/EeRiSy2IHWQQB # 4FHd9Wo9brzLQCbhbb4FapTK0POScy0LebzRWOWfLtyWS+FRBC3kxO126I67CwMb # XRS4YgBqC3U7IGsbzV+fWP01pVeJRzZ1vrv4vdiIYvqTdgNlmFbGjJUwEmPmrokt # q5UreAjMUNLMEXiY6QHFq3N5I+UMY1jslcf7K/ZwDqSlqaquAe+gbnQOAMXDYgb6 # GWsBrLM2WA5E9ObbxsHdxgZqW1NxcWJpSBvjNiOV9t/jqoqpxYwHr5HAvR1xUwm+ # qRKRayRpLlX/Yad4NlvJaH5jvsMrI4bnxTYWVevLvYzc07Xo3dVxW1c+P+WCdjfM # O3bLAvwO7Mw7GRiSNpU8zTbRJu/dS4NWDWZ24u606Cy7qD/qouz89JjkKVYYSFkX # vNp7YOenPf4K6pak/lC3NOLIPlYmnnCLv3RCiaO6wHi4bk1yEBU= # =9dZy # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 14:16:16 PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20231019' of https://github.com/philmd/qemu: (46 commits) ui/input: Constify QemuInputHandler structure hw/net: Declare link using static DEFINE_PROP_LINK() macro hw/dma: Declare link using static DEFINE_PROP_LINK() macro hw/scsi/virtio-scsi: Use VIRTIO_SCSI_COMMON() macro hw/display/virtio-gpu: Use VIRTIO_DEVICE() macro hw/block/vhost-user-blk: Use DEVICE() / VIRTIO_DEVICE() macros hw/virtio/virtio-pmem: Replace impossible check by assertion hw/s390x/css-bridge: Realize sysbus device before accessing it hw/isa: Realize ISA bridge device before accessing it hw/arm/virt: Realize ARM_GICV2M sysbus device before accessing it hw/acpi: Realize ACPI_GED sysbus device before accessing it hw/pci-host/bonito: Do not use SysBus API to map local MMIO region hw/misc/allwinner-dramc: Do not use SysBus API to map local MMIO region hw/misc/allwinner-dramc: Move sysbus_mmio_map call from init -> realize hw/i386/intel_iommu: Do not use SysBus API to map local MMIO region hw/i386/amd_iommu: Do not use SysBus API to map local MMIO region hw/audio/pcspk: Inline pcspk_init() hw/intc/spapr_xive: Do not use SysBus API to map local MMIO region hw/intc/spapr_xive: Move sysbus_init_mmio() calls around hw/ppc/pnv: Do not use SysBus API to map local MMIO region ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-19hw/misc/mips_itu: Make MIPSITUState target agnosticPhilippe Mathieu-Daudé
When prototyping a heterogenous machine including the ITU, we get: include/hw/misc/mips_itu.h:76:5: error: unknown type name 'MIPSCPU' MIPSCPU *cpu0; ^ MIPSCPU is declared in the target specific "cpu.h" header, but we don't want to include it, because "cpu.h" is target specific and its inclusion taints all files including "mips_itu.h", which become target specific too. We can however use the 'ArchCPU *' type in the public header. By keeping the TYPE_MIPS_CPU QOM type check in the link property declaration, QOM core code will still check the property is a correct MIPS CPU. TYPE_MIPS_ITU is still built per-(MIPS)target, but its header can now be included by other targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231009171443.12145-4-philmd@linaro.org>
2023-10-19hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h'Philippe Mathieu-Daudé
We already provide "hw/misc/mips_itu.h" to declare prototype related to MIPSITUState. Move itc_reconfigure() declaration there. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231009171443.12145-3-philmd@linaro.org>
2023-10-19hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folderThomas Huth
The file is obviously related to the raspberrypi machine, so it should reside in hw/arm/ instead of hw/misc/. And while we're at it, also adjust the wildcard in MAINTAINERS so that it covers this file, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231012073458.860187-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-06mac_via: work around underflow in TimeDBRA timing loop in SETUPTIMEKMark Cave-Ayland
The MacOS toolbox ROM calculates the number of branches that can be executed per millisecond as part of its timer calibration. Since modern hosts are considerably quicker than original hardware, the negative counter reaches zero before the calibration completes leading to division by zero later in CALCULATESLOD. Instead of trying to fudge the timing loop (which won't work for TimeDBRA/TimeSCCDB anyhow), use the pattern of access to the VIA1 registers to detect when SETUPTIMEK has finished executing and write some well-known good timer values to TimeDBRA and TimeSCCDB taken from real hardware with a suitable scaling factor. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20231004083806.757242-15-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-10-06q800: add IOSB subsystemMark Cave-Ayland
It is needed because it defines the BIOSConfig area. Co-developed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-ID: <20231004083806.757242-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-10-06q800: add djMEMC memory controllerMark Cave-Ayland
The djMEMC controller is used to store information related to the physical memory configuration. Co-developed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004083806.757242-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-09-11Merge tag 'pull-target-arm-20230908' of ↵Stefan Hajnoczi
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * New CPU type: cortex-a710 * Implement new architectural features: - FEAT_PACQARMA3 - FEAT_EPAC - FEAT_Pauth2 - FEAT_FPAC - FEAT_FPACCOMBINE - FEAT_TIDCP1 * Xilinx Versal: Model the CFU/CFI * Implement RMR_ELx registers * Implement handling of HCR_EL2.TIDCP trap bit * arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE * hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte() * target/arm: Do not use gen_mte_checkN in trans_STGP * arm64: Restore trapless ptimer access # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmT7VEkZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3v7BEACENUKCxsFHRQSLmQkoBCT9 # Lc4SJrGCbVUC6b+4s5ligZSWIoFzp/kY6NPpeRYqFa0DCxozd2T5D81/j7TpSo0C # wUFkZfUq1nGFJ4K5arYcDwhdTtJvvc07YrSbUqufBp6uNGqhR4YmDWPECqBfOlaj # 7bgJM6axsg7FkJJh5zp4cQ4WEfp14MHWRPQWpVTI+9cxNmNymokSVRBhVFkM0Wen # WD4C/nYud8bOxpDfR8GkIqJ+UnUMhUNEhp28QmHdwywgg0zLWOE4ysIxo55cM0+0 # FL3q45PL2e4S24UUx9dkxDBWnKEZ5qpQpPn9F6EhWzfm3n2dqr4uUnfWAEOg6NAi # vnGS9MlL7nZo69OM3h8g7yKDfTKYm2vl9HVZ0ytFA6PLoSnaQyQwli58qnLtiid3 # 17MWPoNQlq6G8tHUTPkrJjdA8XLz0iNPXe5G2kwhuM/S0Lv7ORzDc2pq4qBYLvIw # 9nV0oUWqzyE7zH6bRKxbbPw2sMI7c8qQr9QRyZeLHL7HdcY5ExvX9FH+qii5JDR/ # fZohi1pBoNNwYYTeSRnxgHiQ7OizYq0xQJhrdqcFF9voytZj1yZEZ0mp6Tq0/CIj # YkC/vEyLYBqgrJ2JeUjbV3h1RIzQcVaXxnxwGsyMyceACd6MNMmdbjR7bZk0lNIu # kh+aFEdKajPp56UseJiKBQ== # =5Shq # -----END PGP SIGNATURE----- # gpg: Signature made Fri 08 Sep 2023 13:05:13 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm: (26 commits) arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE target/arm: Enable SCTLR_EL1.TIDCP for user-only target/arm: Implement FEAT_TIDCP1 target/arm: Implement HCR_EL2.TIDCP target/arm: Implement cortex-a710 target/arm: Implement RMR_ELx arm64: Restore trapless ptimer access target/arm: Do not use gen_mte_checkN in trans_STGP hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO hw/misc: Introduce a model of Xilinx Versal's CFU_APB hw/misc: Introduce the Xilinx CFI interface hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte() target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE target/arm: Inform helpers whether a PAC instruction is 'combined' target/arm: Implement FEAT_Pauth2 ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-09-08hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REGFrancisco Iglesias
Introduce a model of Xilinx Versal's Configuration Frame broadcast controller (CFRAME_BCAST_REG). Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230831165701.2016397-7-francisco.iglesias@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-08hw/misc: Introduce a model of Xilinx Versal's CFRAME_REGFrancisco Iglesias
Introduce a model of Xilinx Versal's Configuration Frame controller (CFRAME_REG). Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20230831165701.2016397-6-francisco.iglesias@amd.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>