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path: root/hw/riscv/virt.c
AgeCommit message (Expand)Author
2021-10-28hw/riscv: virt: Use the PLIC config helper functionAlistair Francis
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis
2021-10-22hw/riscv: virt: Use machine->ram as the system memoryMingwang Li
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-09-01hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell
2021-09-01hw/riscv: virt: Move flash node to rootBin Meng
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng
2021-06-08hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth
2021-03-22hw/riscv: allow ramfb on virtAsherah Connor
2021-03-22hw/riscv: Add fw_cfg support to virtAsherah Connor
2021-03-10hw/riscv: migrate fdt field to generic MachineStateAlex Bennée
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis
2020-12-17hw/riscv: virt: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini
2020-11-03hw/riscv: virt: Allow passing custom DTBAnup Patel
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-08-25hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra
2020-07-13hw/riscv: virt: Sort the SoC memmap table entriesBin Meng
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster
2020-06-15sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster
2020-06-15qdev: Convert uses of qdev_create() manuallyMarkus Armbruster
2020-06-15qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster
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