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path: root/hw/riscv/sifive_u.c
AgeCommit message (Expand)Author
2023-03-01hw/riscv: Move the dtb load bits outside of create_fdt()Bin Meng
2023-03-01hw/riscv: Skip re-generating DT nodes for a given DTBBin Meng
2023-02-16hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza
2023-02-16hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza
2023-01-20hw/riscv/sifive_u.c: simplify create_fdt()Daniel Henrique Barboza
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza
2023-01-20hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()Daniel Henrique Barboza
2023-01-20hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza
2023-01-20hw/riscv/sifive_u: use 'fdt' from MachineStateDaniel Henrique Barboza
2023-01-20hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza
2023-01-06hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"Bin Meng
2022-10-17hw/riscv: set machine->fdt in sifive_u_machine_init()Daniel Henrique Barboza
2022-05-24hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow
2022-05-24hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng
2022-01-08hw/riscv: Use error_fatal for SoC realisationAlistair Francis
2021-12-15hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster
2021-12-15hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis
2021-10-22hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell
2021-07-15hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng
2021-07-15hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng
2021-06-08hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis
2021-01-16hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis
2020-12-17hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini
2020-11-03hw/riscv: sifive_u: Allow passing custom DTBAnup Patel
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis
2020-09-22sifive_u: Register "start-in-flash" as class propertyEduardo Habkost
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost
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