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path: root/hw/pci-bridge/cxl_root_port.c
AgeCommit message (Expand)Author
2024-04-25hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell
2024-03-12bulk: Access existing variables initialized to &S->F when availablePhilippe Mathieu-Daudé
2024-02-14hw/cxl: Standardize all references on CXL r3.1 and minor updatesJonathan Cameron
2023-11-07hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExtJonathan Cameron
2023-03-07hw/pci-bridge/cxl_root_port: Wire up MSIJonathan Cameron
2023-03-07hw/pci-bridge/cxl_root_port: Wire up AERJonathan Cameron
2022-12-16pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase resetPeter Maydell
2022-05-13hw/cxl/rp: Add a root portBen Widawsky