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2021-03-13hw/mips/gt64xxx: Trace accesses to ISD registersPhilippe Mathieu-Daudé
Trace all accesses to Internal Space Decode (ISD) registers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20210309142630.728014-6-f4bug@amsat.org>
2021-03-13hw/mips/gt64xxx: Rename trace events related to interrupt registersPhilippe Mathieu-Daudé
We want to trace all register accesses. First rename the current gt64120_read / gt64120_write events with '_intreg' suffix, as they are restricted to interrupt registers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20210309142630.728014-5-f4bug@amsat.org>
2021-03-13hw/mips/gt64xxx: Fix typos in qemu_log_mask() formatsPhilippe Mathieu-Daudé
Fix the following typos: - GT_PCI1_CFGDATA is not a timer register but a PCI one, - zero-padding flag is out of the format Fixes: 641ca2bfcd5 ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20210309142630.728014-4-f4bug@amsat.org>
2021-03-13hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlersPhilippe Mathieu-Daudé
The ISD MemoryRegion is implemented for 32-bit accesses. Simplify it by setting the MemoryRegionOps::impl min/max access size fields. Since the region is registered with a size of 0x1000 bytes, we can remove the hwaddr mask. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20210309142630.728014-3-f4bug@amsat.org>
2021-03-13hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize()Philippe Mathieu-Daudé
The ISD I/O region belongs to the TYPE_GT64120_PCI_HOST_BRIDGE, so initialize it before it is realized, not after. Rename the region as 'gt64120-isd' so it is clearer to realize it belongs to the GT64120 in the memory tree view. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20210309142630.728014-2-f4bug@amsat.org>
2021-03-11Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-docs-xen-updates-100321-2' into staging Testing, guest-loader and other misc tweaks - add warning text to quickstart example - add CFI tests to CI - use --arch-only for docker pre-requisites - fix .editorconfig for emacs - add guest-loader for Xen-like hypervisor testing - move generic-loader docs into manual proper - move semihosting out of hw/ # gpg: Signature made Wed 10 Mar 2021 15:35:31 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-docs-xen-updates-100321-2: semihosting: Move hw/semihosting/ -> semihosting/ semihosting: Move include/hw/semihosting/ -> include/semihosting/ tests/avocado: add boot_xen tests docs: add some documentation for the guest-loader docs: move generic-loader documentation into the main manual hw/core: implement a guest-loader to support static hypervisor guests device_tree: add qemu_fdt_setprop_string_array helper hw/riscv: migrate fdt field to generic MachineState hw/board: promote fdt from ARM VirtMachineState to MachineState .editorconfig: update the automatic mode setting for Emacs tests/docker: Use --arch-only when building Debian cross image gitlab-ci.yml: Add jobs to test CFI flags gitlab-ci.yml: Allow custom # of parallel linkers tests/docker: add a test-tcg for building then running check-tcg docs/system: add a gentle prompt for the complexity to come Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé
We want to move the semihosting code out of hw/ in the next patch. This patch contains the mechanical steps, created using: $ git mv include/hw/semihosting/ include/ $ sed -i s,hw/semihosting,semihosting, $(git grep -l hw/semihosting) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210226131356.3964782-2-f4bug@amsat.org> Message-Id: <20210305135451.15427-2-alex.bennee@linaro.org>
2021-03-10Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20210310' into staging target-arm queue: * Add new mps3-an547 board * target/arm: Restrict v7A TCG cpus to TCG accel * Implement a Xilinx CSU DMA model * hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() # gpg: Signature made Wed 10 Mar 2021 13:56:20 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210310: (54 commits) hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_ hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips hw/ssi: xilinx_spips: Clean up coding convention issues hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI hw/arm: xlnx-zynqmp: Clean up coding convention issues hw/dma: Implement a Xilinx CSU DMA model target/arm: Restrict v7A TCG cpus to TCG accel tests/qtest/sse-timer-test: Test counter scaling changes tests/qtest/sse-timer-test: Test the system timer tests/qtest/sse-timer-test: Add simple test of the SSE counter docs/system/arm/mps2.rst: Document the new mps3-an547 board hw/arm/mps2-tz: Add new mps3-an547 board hw/arm/mps2-tz: Make initsvtor0 setting board-specific hw/arm/mps2-tz: Support running APB peripherals on different clock hw/misc/mps2-scc: Implement changes for AN547 hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate hw/arm/mps2-tz: Make UART overflow IRQ board-specific hw/arm/armsse: Add SSE-300 support ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-08clock: Add ClockEvent parameter to callbacksPeter Maydell
The Clock framework allows users to specify a callback which is called after the clock's period has been updated. Some users need to also have a callback which is called before the clock period is updated. As the first step in adding support for notifying Clock users on pre-update events, add an argument to the ClockCallback to specify what event is being notified, and add an argument to the various functions for registering a callback to specify which events are of interest to that callback. Note that the documentation update renders correct the previously incorrect claim in 'Adding a new clock' that callbacks "will be explained in a following section". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-2-peter.maydell@linaro.org
2021-03-07esp: rename existing ESP QOM type to SYSBUS_ESPMark Cave-Ayland
The existing ESP QOM type currently represents a sysbus device with an embedded ESP state. Rename the type to SYSBUS_ESP accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-3-mark.cave-ayland@ilande.co.uk>
2021-02-21vt82c686: Move creation of ISA devices to the ISA bridgeBALATON Zoltan
Currently the ISA devices that are part of the VIA south bridge, superio chip are wired up by board code. Move creation of these ISA devices to the VIA ISA bridge model so that board code does not need to access ISA bus. This also allows vt82c686b-superio to be made internal to vt82c686 which allows implementing its configuration via registers in subseqent commits. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <bf9400cc8e4ddd3129aa5678de4d3cf38384805f.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Fix SMBus IO base and configuration registersBALATON Zoltan
The base address of the SMBus io ports and its enabled status is set by registers in the PCI config space but this was not correctly emulated. Instead the SMBus registers were mapped on realize to the base address set by a property to the address expected by fuloong2e firmware. Fix the base and config register handling to more closely model hardware which allows to remove the property and allows the guest to control this mapping. Do all this in reset instead of realize so it's correctly updated on reset. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <f2ca2ad5f08ba8cee07afd9d67b4e75cda21db09.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21hw/mips/boston: Use bootloader helper to set GCRsJiaxun Yang
Translate embedded assembly into IO writes which is more readable. Also hardcode cm_base at boot time instead of reading from CP0. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210127065424.114125-5-jiaxun.yang@flygoat.com> [PMD: Kept code comments] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21hw/mips/boston: Use bl_gen_kernel_jump to generate bootloadersJiaxun Yang
Replace embedded binary with generated code. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201215064507.30148-2-jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Split original patch as one for each machine (here boston)] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21hw/mips/fuloong2e: Use bl_gen_kernel_jump to generate bootloadersJiaxun Yang
Replace embedded binary with generated code. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201215064507.30148-2-jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Split original patch as one for each machine (here fuloong2e)] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21hw/mips: Add a bootloader helperJiaxun Yang
Add a bootloader helper to generate simple bootloaders for kernel. It can help us reduce inline hex hack and also keep MIPS release 6 compatibility easier. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210127065424.114125-2-jiaxun.yang@flygoat.com> [PMD: Restricted bl_reg enum to C source, inverted bl_gen_write() args, added license in hw/mips/bootloader.h] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21hw/mips: loongson3: Drop 'struct MemmapEntry'Bin Meng
There is already a MemMapEntry type defined in hwaddr.h. Let's drop the loongson3 defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210122122404.11970-1-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana
we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the TCG fields to TCG-only builds, is to move all tcg cpu operations into a separate header file, which is only included by TCG, target-specific code. This leaves just a NULL pointer in the cpu.h for the non-TCG builds. This also tidies up the code in all targets a bit, having all TCG cpu operations neatly contained by a dedicated data struct. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-16-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY] avoiding its use in headers used by common_ss code (should be poisoned). Note: need to be careful with the use of CONFIG_USER_ONLY, Message-Id: <20210204163931.7358-11-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-14docs/system: Remove deprecated 'fulong2e' machine aliasPhilippe Mathieu-Daudé
The 'fulong2e' machine alias has been marked as deprecated since QEMU v5.1 (commit c3a09ff68dd, the machine is renamed 'fuloong2e'). Time to remove it now. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20210106184602.3771551-1-f4bug@amsat.org>
2021-01-14hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()Philippe Mathieu-Daudé
Directly check if the CPU supports 64-bit with the recently added cpu_type_is_64bit() helper (inlined). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-6-f4bug@amsat.org>
2021-01-04hw/mips/fuloong2e: Correct cpuclock in PROM environmentJiaxun Yang
Missed in 3ca7639ff00 ("hw/mips/fuloong2e: Set CPU frequency to 533 MHz"), we need to tell the kernel the correct clock. Fixes: 3ca7639ff00 ("hw/mips/fuloong2e: Set CPU frequency to 533 MHz"). Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201224031750.52146-7-jiaxun.yang@flygoat.com> [PMD: Reworded] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips/fuloong2e: Remove unused env entryJiaxun Yang
modetty is not handled by kernel and the parameter here seems unreasonable. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201224031750.52146-6-jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Do not remove busclock] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips/fuloong2e: Replace faulty documentation linksJiaxun Yang
Websites are downing, but GitHub may last forever. Loongson even doesn't recogonize 2E as their products nowadays.. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201224031750.52146-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips/fuloong2e: Remove define DEBUG_FULOONG2E_INITJiaxun Yang
Seems useless.... Fixes: 051c190bce5 ("MIPS: Initial support of fulong mini pc (machine construction)") Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Message-Id: <20201224031750.52146-2-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips: Use address translation helper to handle ENVP_ADDRJiaxun Yang
It will signed extend vaddr properly. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201215064200.28751-4-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips/malta: Use address translation helper to calculate bootloader_run_addrJiaxun Yang
So it will sign extend adresses properly. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201215064200.28751-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips: Make bootloader addresses unsignedJiaxun Yang
Address should be unsigned anyway, otherwise it may carry calculations wrongly. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201215064200.28751-2-jiaxun.yang@flygoat.com> [PMD: Fixed typo and convert hw/mips/mipssim.c too] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips: Add Loongson-3 machine supportHuacai Chen
Add Loongson-3 based machine support, it use liointc as the interrupt controler and use GPEX as the pci controller. Currently it can work with both TCG and KVM. As the machine model is not based on any exiting physical hardware, the name of the machine is "loongson3-virt". It may be superseded in future by a real machine model. If this happens, then a regular deprecation procedure shall occur for "loongson3-virt" machine. We now already have a full functional Linux kernel (based on Linux-5.4.x LTS) here: https://github.com/chenhuacai/linux Of course the upstream kernel is also usable (the kvm host side and guest side have both been upstream in Linux-5.9): https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git How to use QEMU/Loongson-3? 1, Download kernel source from the above URL; 2, Build a kernel with arch/mips/configs/loongson3_defconfig; 3, Boot a Loongson-3A4000 host with this kernel (for KVM mode); 4, Build QEMU-master with this patchset; 5, modprobe kvm (only necessary for KVM mode); 6, Use QEMU with TCG: qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ... Use QEMU with KVM: qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ... The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically. Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201221110538.3186646-5-chenhuacai@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Set TYPE_LOONGSON_MACHINE instance_size in TypeInfo, select FW_CFG_MIPS in Kconfig] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips: Add Loongson-3 boot parameter helpersHuacai Chen
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) helpers first. Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201221110538.3186646-4-chenhuacai@kernel.org> [PMD: Fixed typo] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips: Implement fw_cfg_arch_key_name()Huacai Chen
Implement fw_cfg_arch_key_name(), which returns the name of a mips-specific key. Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1600742967-12933-7-git-send-email-chenhc@lemote.com> [PMD: Add FW_CFG_MIPS Kconfig selector] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04vt82c686: Remove legacy vt82c686b_pm_init() functionBALATON Zoltan
Remove legacy vt82c686b_pm_init() function and also rename VT82C686B_PM type name to match other device names. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <a70982b32f11222d335385b90749abb6cf2e2cce.1609584216.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04vt82c686: Remove legacy vt82c686b_isa_init() functionBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <58d7585f979f154b1f1e69fdc026eed6dbc7996f.1609584216.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04vt82c686: Remove vt82c686b_[am]c97_init() functionsBALATON Zoltan
These are legacy init functions that are just equivalent to directly calling pci_create_simple so do that instead. Also rename objects to lower case via-ac97 and via-mc97 matching naming of other devices. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1c4373c8aeb6c4fb2a8df2c864b0e91a977a3d7b.1609584216.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw: Use the PCI_SLOT() macro from 'hw/pci/pci.h'Philippe Mathieu-Daudé
We already have a generic PCI_SLOT() macro in "hw/pci/pci.h" to extract the PCI slot identifier, use it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Paul Durrant <paul@xen.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20201012124506.3406909-5-philmd@redhat.com>
2020-12-13hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit()Philippe Mathieu-Daudé
PTC field has 8 bits, PVPE has 4. We plan to use the "hw/registerfields.h" API with MIPS CPU definitions (target/mips/cpu.h). Meanwhile we use magic 8 and 4. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-6-f4bug@amsat.org>
2020-12-13hw/mips/malta: Do not initialize MT registers if MT ASE absentPhilippe Mathieu-Daudé
Do not initialize MT-related config register if the MT ASE is not present. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-5-f4bug@amsat.org>
2020-12-13target/mips: Introduce ase_mt_available() helperPhilippe Mathieu-Daudé
Instead of accessing CP0_Config3 directly and checking the 'Multi-Threading Present' bit, introduce an helper to simplify code review. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-3-f4bug@amsat.org>
2020-12-13hw/mips: Move address translation helpers to target/mips/Philippe Mathieu-Daudé
Address translation is an architectural thing (not hardware related). Move the helpers from hw/ to target/. As physical address and KVM are specific to system mode emulation, restrict this file to softmmu, so it doesn't get compiled for user-mode emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-2-f4bug@amsat.org>
2020-12-13target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()Philippe Mathieu-Daudé
As cpu_supports_isa() / cpu_supports_cps_smp() take a 'cpu_type' name argument, rename them cpu_type_supports_FEAT(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201207215257.4004222-2-f4bug@amsat.org>
2020-12-10vl: extract softmmu/datadir.cPaolo Bonzini
Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-10mips: do not use ram_size globalPaolo Bonzini
Use the machine properties or loader parameters instead. Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-10mips: remove bios_namePaolo Bonzini
Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201026143028.3034018-9-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-11-09hw/mips/boston: Fix memory leak in boston_fdt_filter() error-handling pathsPeter Maydell
Coverity points out that the error-handling paths in the boston_fdt_filter() function don't free the fdt that was allocated. Fix the leak by using g_autofree. Fixes: Coverity CID 1432275 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201106175823.1650-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-11-03hw/mips/boston: Fix Lesser GPL version numberChetan Pant
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201023122633.19466-1-chetan4windows@gmail.com> [PMD: Added hw/mips/ prefix in subject] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-11-03hw/mips: Fix Lesser GPL version numberChetan Pant
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201016143509.26692-1-chetan4windows@gmail.com> [PMD: Split hw/ vs target/] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-11-03hw/mips: Remove the 'r4k' machinePhilippe Mathieu-Daudé
We deprecated the support for the 'r4k' machine for the 5.0 release (commit d32dc61421), which means that our deprecation policy allows us to drop it in release 5.2. Remove the code. To repeat the rationale from the deprecation note: - this virtual machine has no specification - the Linux kernel dropped support for it 10 years ago Users are recommended to use the Malta board instead. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> ACKed-by: Peter Krempa <pkrempa@redhat.com> Message-Id: <20201102201311.2220005-1-f4bug@amsat.org>
2020-10-17hw/mips: Remove exit(1) in case of missing ROMPavel Dovgalyuk
This patch updates MIPS-based machines to allow starting them without ROM. In this case CPU starts to execute instructions from the empty memory, but QEMU allows introspecting the machine configuration. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <159531210571.24117.231100997794891819.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTONEduardo Habkost
This will make the type name constant consistent with the name of the type checking macro. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200902224311.1321159-19-ehabkost@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)Philippe Mathieu-Daudé
Instead of using a INITRD_PAGE_MASK definition, use the simpler INITRD_PAGE_SIZE one which allows us to simplify the code by using directly the self-explicit ROUND_UP() macro. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200927163943.614604-3-f4bug@amsat.org>
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-29 10:03:41 +0000