aboutsummaryrefslogtreecommitdiff
path: root/hw/m68k
AgeCommit message (Collapse)Author
2022-03-09mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQsMark Cave-Ayland
The mos6522 datasheet describes how the control lines IRQs are edge-triggered according to the configuration in the PCR register. Implement the logic according to the datasheet so that the interrupt bits in IFR are latched when the edge is detected, and cleared when reading portA/portB or writing to IFR as necessary. To maintain bisectibility this change also updates the SCSI, SCSI data, Nubus and VIA2 60Hz/1Hz clocks in the q800 machine to be negative edge-triggered as confirmed by the PCR programming in all of Linux, NetBSD and MacOS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-01-20m68k: virt: correctly set the initial PCLaurent Vivier
According to QEMU parameter, set initial PC to the entry of the loaded kernel. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220115203725.3834712-4-laurent@vivier.eu>
2022-01-09q800: fix segfault with invalid MacROMLaurent Vivier
"qemu-system-m68k -M q800 -bios /dev/null" crashes with a segfault in q800_init(). This happens because the code doesn't check that rom_ptr() returned a non-NULL pointer . To avoid NULL pointer, don't allow 0 sized file and use bios_size with rom_ptr(). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/756 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220107105049.961489-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-09hw: m68k: Add virt compat machine type for 7.0Laurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20211218114340.1856757-1-laurent@vivier.eu>
2021-11-09Merge tag 'm68k-for-6.2-pull-request' of git://github.com/vivier/qemu-m68k ↵Richard Henderson
into staging m68k pull request 20211109 Add virt machine types for 6.1 and 6.2 # gpg: Signature made Tue 09 Nov 2021 12:14:39 PM CET # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] * tag 'm68k-for-6.2-pull-request' of git://github.com/vivier/qemu-m68k: hw: m68k: virt: Add compat machine for 6.2 hw: m68k: virt: Add compat machine for 6.1 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-09hw: m68k: virt: Add compat machine for 6.2Laurent Vivier
Add the missing machine type for m68k/virt Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211106194158.4068596-3-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-11-09hw: m68k: virt: Add compat machine for 6.1Laurent Vivier
Add the missing machine type for m68k/virt Cc: qemu-stable@nongnu.org Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211106194158.4068596-2-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-11-09hw/m68k: Fix typo in SPDX tagPhilippe Mathieu-Daudé
Fix 'Identifer' -> 'Identifier' typo. Cc: Laurent Vivier <laurent@vivier.eu> Fixes: 8c6df16ff60 ("hw/char: add goldfish-tty") Fixes: 87855593903 ("hw/intc: add goldfish-pic") Fixes: 2fde99ee312 ("m68k: add an interrupt controller") Fixes: 0791bc02b8f ("m68k: add a system controller") Fixes: e1cecdca559 ("m68k: add Virtual M68k Machine") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211103105311.3399293-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: drop 8-bit graphic_depth check for Apple 21 inch displayMark Cave-Ayland
The graphic_depth check is no longer required since commit df8abbbadf ("macfb: add common monitor modes supported by the MacOS toolbox ROM") which introduced code in macfb_common_realize() to only allow the resolutions/depths provided in macfb_mode_table to be specified for each display type. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Fixes: df8abbbadf ("macfb: add common monitor modes supported by the MacOS toolbox ROM") Message-Id: <20211020141810.7875-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: add NMI handlerMark Cave-Ayland
This allows the programmer's switch to be triggered via the monitor for debugging purposes. Since the CPU level 7 interrupt is level-triggered, use a timer to hold the NMI active for 100ms before releasing it again. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewied-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: wire up remaining IRQs in classic modeMark Cave-Ayland
Explicitly wire up the remaining IRQs in classic mode to enable the use of g_assert_not_reached() in the default case to detect any unexpected IRQs. Add a comment explaining the IRQ routing differences in A/UX mode based upon the comments in NetBSD (also noting that at least A/UX 3.0.1 still uses classic mode). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic modeMark Cave-Ayland
When the hardware is operating in classic mode the SONIC on-board Ethernet IRQ is routed to nubus IRQ 9 instead of directly to the CPU at level 3. This does not affect the framebuffer which although it exists in slot 9, has its own dedicated IRQ on the Quadra 800 hardware. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: wire up auxmode GPIO to GLUEMark Cave-Ayland
This enables the GLUE logic to change its CPU level IRQ routing depending upon whether the hardware has been configured for A/UX mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQsMark Cave-Ayland
In order to allow dynamic routing of IRQs to different IRQ levels on the CPU depending upon port B bit 6, use GLUE IRQ numbers and map them to the the corresponding CPU IRQ level accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-20q800: move VIA1 IRQ from level 1 to level 6Mark Cave-Ayland
On a Quadra 800 machine Linux sets via_alt_mapping to 1 and clears port B bit 6 to ensure that the VIA1 IRQ is delivered at level 6 rather than level 1. Even though QEMU doesn't yet emulate this behaviour, Linux still installs the VIA1 level 1 IRQ handler regardless of the value of via_alt_mapping which is why the kernel has been able to boot until now. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08q800: wire macfb IRQ to separate video interrupt on VIA2Mark Cave-Ayland
Whilst the in-built Quadra 800 framebuffer exists within the Nubus address space for slot 9, it has its own dedicated interrupt on VIA2. Force the macfb device to occupy slot 9 in the q800 machine and wire its IRQ to the separate video interrupt since this is what is expected by the MacOS interrupt handler. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-14-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: add common monitor modes supported by the MacOS toolbox ROMMark Cave-Ayland
The monitor modes table is found by experimenting with the Monitors Control Panel in MacOS and analysing the reads/writes. From this it can be found that the mode is controlled by writes to the DAFB_MODE_CTRL1 and DAFB_MODE_CTRL2 registers. Implement the first block of DAFB registers as a register array including the existing sense register, the newly discovered control registers above, and also the DAFB_MODE_VADDR1 and DAFB_MODE_VADDR2 registers which are used by NetBSD to determine the current video mode. These experiments also show that the offset of the start of video RAM and the stride can change depending upon the monitor mode, so update macfb_draw_graphic() and both the BI_MAC_VADDR and BI_MAC_VROW bootinfo for the q800 machine accordingly. Finally update macfb_common_realize() so that only the resolution and depth supported by the display type can be specified on the command line, and add an error hint showing the list of supported resolutions and depths if the user tries to specify an invalid display mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: add qdev property to specify display typeMark Cave-Ayland
Since the available resolutions and colour depths are determined by the attached display type, add a qdev property to allow the display type to be specified. The main resolutions of interest are high resolution 1152x870 with 8-bit colour and SVGA resolution up to 800x600 with 24-bit colour so update the q800 machine to allow high resolution mode if specified and otherwise fall back to SVGA. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-29q800: configure nubus available slots for Quadra 800Mark Cave-Ayland
Slot 0x9 is reserved for use by the in-built framebuffer whilst only slots 0xc, 0xd and 0xe physically exist on the Quadra 800. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210924073808.1041-21-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-29q800: wire up nubus IRQsMark Cave-Ayland
Nubus IRQs are routed to the CPU through the VIA2 device so wire up the IRQs using gpios accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210924073808.1041-20-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-29nubus-bridge: embed the NubusBus object directly within nubus-bridgeMark Cave-Ayland
Since nubus-bridge is a container for NubusBus then it should be embedded directly within the bridge device using qbus_create_inplace(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210924073808.1041-17-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-29nubus: move NubusBus from mac-nubus-bridge to nubus-bridgeMark Cave-Ayland
Now that Nubus has its own address space rather than mapping directly into the system bus, move the Nubus reference from MacNubusBridge to NubusBridge. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210924073808.1041-16-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-29nubus: move nubus to its own 32-bit address spaceMark Cave-Ayland
According to "Designing Cards and Drivers for the Macintosh Family" the Nubus has its own 32-bit address space based upon physical slot addressing. Move Nubus to its own 32-bit address space and then use memory region aliases to map available slot and super slot ranges into the q800 system address space via the Macintosh Nubus bridge. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210924073808.1041-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: remove explicit viaN prefix from VIA IRQ gpiosMark Cave-Ayland
Now that q800 VIA1 and VIA2 are completely separate devices there is no need to add a specific device prefix to ensure that the IRQ lines remain separate. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210830102447.10806-11-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: remove mac_via deviceMark Cave-Ayland
Remove the mac_via device and wire up both q800 VIA1 and VIA2 directly for the m68k q800 machine. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: move ADB variables to MOS6522Q800VIA1StateMark Cave-Ayland
The ADB is accessed using clock and data pins on q800 VIA1 port B and so can be moved to MOS6522Q800VIA1State. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210830102447.10806-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-07-26bitops.h: revert db1ffc32dd ("qemu/bitops.h: add bitrev8 implementation")Mark Cave-Ayland
Commit db1ffc32dd ("qemu/bitops.h: add bitrev8 implementation") introduced a bitrev8() function to reverse the bit ordering required for storing the MAC address in the q800 PROM. This function is not required since QEMU implements its own revbit8() function which does exactly the same thing. Remove the extraneous bitrev8() function and switch its only caller in hw/m68k/q800.c to use revbit8() instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210725110557.3007-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-02hw/m68k/q800: fix PROM checksum and MAC address storageMark Cave-Ayland
The checksum used by MacOS to validate the PROM content is an exclusive-OR rather than a sum over the corresponding bytes. In addition the MAC address must be stored in bit-reversed format as indicated in comments in Linux's macsonic.c. With the PROM contents fixed MacOS starts to probe the device registers when AppleTalk is enabled in the Control Panel. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Finn Thain <fthain@linux-m68k.org> Message-Id: <20210625065401.30170-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-02hw/m68k/q800: move PROM and checksum calculation from dp8393x device to boardMark Cave-Ayland
This is in preparation for each board to have its own separate bit storage format and checksum for storing the MAC address. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Finn Thain <fthain@linux-m68k.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210625065401.30170-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-06-15softmmu/memory: Pass ram_flags to memory_region_init_ram_shared_nomigrate()David Hildenbrand
Let's forward ram_flags instead, renaming memory_region_init_ram_shared_nomigrate() into memory_region_init_ram_flags_nomigrate(). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> for memory backend and machine core Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210510114328.21835-6-david@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth
Stop including exec/address-spaces.h in files that don't need it. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-5-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-02Do not include cpu.h if it's not really necessaryThomas Huth
Stop including cpu.h in files that don't need it. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-4-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-02Do not include sysemu/sysemu.h if it's not really necessaryThomas Huth
Stop including sysemu/sysemu.h in files that don't need it. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-2-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-02hw: Do not include hw/irq.h if it is not necessaryThomas Huth
Many files include hw/irq.h without needing it. Remove the superfluous include statements. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210327050236.2232347-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-02hw: Remove superfluous includes of hw/hw.hThomas Huth
The include/hw/hw.h header only has a prototype for hw_error(), so it does not make sense to include this in files that do not use this function. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210326151848.2217216-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-15m68k: add Virtual M68k MachineLaurent Vivier
The machine is based on Goldfish interfaces defined by Google for Android simulator. It uses Goldfish-rtc (timer and RTC), Goldfish-pic (PIC) and Goldfish-tty (for serial port and early tty). The machine is created with 128 virtio-mmio bus, and they can be used to use serial console, GPU, disk, NIC, HID, ... Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210312214145.2936082-6-laurent@vivier.eu>
2021-03-07esp: rename existing ESP QOM type to SYSBUS_ESPMark Cave-Ayland
The existing ESP QOM type currently represents a sysbus device with an embedded ESP state. Rename the type to SYSBUS_ESP accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-3-mark.cave-ayland@ilande.co.uk>
2021-02-11m68k: import bootinfo headers from linuxLaurent Vivier
Copy bootinfo.h and bootinfo-mac.h from arch/m68k/include/uapi/asm/ to include/standard-headers/asm-m68k/ Imported from linux v5.9 but didn't change since v4.14 (header update) and since v4.10 (content update). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201220112615.933036-2-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-19hw/m68k/next-cube: Add vmstate for NeXTPC devicePeter Maydell
Add the vmstate for the new NeXTPC devic; this is in theory a migration compatibility break, but this machine doesn't have working migration currently anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-11-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Remove unused fields from NeXTStatePeter Maydell
The fields scsi_irq, scsi_dma, scsi_reset and fd_irq in NeXTState are all unused, except in commented out "this should do something like this" code. Remove the unused fields. As and when the functionality that might use them is added, we can put in the correct kind of wiring (which might or might not need to be a qemu_irq, but which in any case will need to be in the NeXTPC device, not in NeXTState). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-10-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move rtc into NeXTPC structPeter Maydell
Move the rtc into the NeXTPC struct. Since this is the last use of the 'backdoor' NextState pointer we can now remove that. Probably the RTC should be its own device at some point: in hardware there is a separate MCS1850 RTC chip connected to the Peripheral Controller via a 1-bit serial interface. That goes beyond the remit of the current refactoring, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-9-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Make next_irq GPIO inputs to NEXT_PC devicePeter Maydell
Make the next_irq function be GPIO inputs to the NEXT_PC device, rather than a freestanding set of qemu_irq lines. This fixes a minor Coverity issue where it correctly points out the trivial memory leak of the memory allocated in the call to qemu_allocate_irqs(). Fixes: CID 1421962 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-8-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move int_status and int_mask to NeXTPC structPeter Maydell
All the code which accesses int_status and int_mask is now doing so via the NeXTPC->NeXTState indirection, so we can move these fields into the NeXTPC struct where they belong. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-7-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Make next_irq take NeXTPC* as its opaquePeter Maydell
Make the next_irq function take a NeXTPC* as its opaque rather than the M68kCPU*. This will make it simpler to turn the next_irq function into a gpio input line of the NeXTPC device in the next commit. For this to work we have to pass the CPU to the NeXTPC device via a link property, in the same way we do in q800.c (and for the same reason). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-6-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move scr_ops into NeXTPC devicePeter Maydell
Move the registers handled by the scr_ops struct into the NeXTPC device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-5-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move mmio_ops into NeXTPC devicePeter Maydell
Move the registers handled by the mmio_ops struct into the NeXTPC device. This allows us to also move the scr1 and scr2 data fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-4-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move register/interrupt functionality into a devicePeter Maydell
Currently the next-cube board code open-codes a lot of handling of interrupts and some miscellaneous registers. Move this into a proper QOM device. In the real hardware this functionality seems to be the responsibility of the Peripheral Controller (PC) chip, so name the device that. There are several different things that will need to be moved into this device: * the mmio_iops register set * the scr_ops register set * the next_irq IRQ handling To ease review, we structure the change as a sequence of commits: in this first commit we create the skeleton of the NeXTPC device with no content, but with a backdoor pointer to the NeXTState machine's state struct so we can move parts of the code and still have refactored and non-refactored code using the same struct data fields. Further commits will move functionality into the new device piece by piece. At the end we will be able to remove the backdoor pointer because all the data fields will be in the NeXTPC struct and not the NeXTState struct. We'll add the VMState for the new device at the end of all that; this is in theory a migration compatibility break but this machine does not currently support migration at all anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-3-peter.maydell@linaro.org> [huth: Add a comment in front of struct NeXTPC] Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Make next_irq() function staticPeter Maydell
The next_irq() function is global, but isn't actually used anywhere outside next-cube.c. Make it static. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-2-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2020-12-12hw/m68k/q800.c: Make the GLUE chip an actual QOM devicePeter Maydell
The handling of the GLUE (General Logic Unit) device is currently open-coded. Make this into a proper QOM device. This minor piece of modernisation gets rid of the free floating qemu_irq array 'pic', which Coverity points out is technically leaked when we exit the machine init function. (The replacement glue device is not leaked because it gets added to the sysbus, so it's accessible via that.) Fixes: Coverity CID 1421883 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201106235109.7066-3-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-12hw/m68k/q800: Don't connect two qemu_irqs directly to the same inputPeter Maydell
The q800 board code connects both of the IRQ outputs of the ESCC to the same pic[3] qemu_irq. Connecting two qemu_irqs outputs directly to the same input is not valid as it produces subtly wrong behaviour (for instance if both the IRQ lines are high, and then one goes low, the PIC input will see this as a high-to-low transition even though the second IRQ line should still be holding it high). This kind of wiring needs an explicitly created OR gate; add one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201106235109.7066-2-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-30 16:42:34 +0000