aboutsummaryrefslogtreecommitdiff
path: root/accel
AgeCommit message (Expand)Author
2018-12-26tcg: Add RISC-V cpu signal handlerAlistair Francis
2018-12-11accel: register global_props like machine globalsMarc-André Lureau
2018-10-31cputlb: Remove tlb_c.pending_flushesRichard Henderson
2018-10-31cputlb: Filter flushes on already clean tlbsRichard Henderson
2018-10-31cputlb: Count "partial" and "elided" tlb flushesRichard Henderson
2018-10-31cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidxRichard Henderson
2018-10-31cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_workRichard Henderson
2018-10-31cputlb: Move env->vtlb_index to env->tlb_d.vindexRichard Henderson
2018-10-31cputlb: Split large page tracking per mmu_idxRichard Henderson
2018-10-31cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flushRichard Henderson
2018-10-31cputlb: Remove tcg_enabled hack from tlb_flush_nocheckRichard Henderson
2018-10-31cputlb: Move tlb_lock to CPUTLBCommonRichard Henderson
2018-10-19Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2018-10-19target-i386 : add coalesced_pio APIPeng Hao
2018-10-18cputlb: read CPUTLBEntry.addr_write atomicallyEmilio G. Cota
2018-10-18tcg: Split CONFIG_ATOMIC128Richard Henderson
2018-10-18tcg: Add tlb_index and tlb_entry helpersRichard Henderson
2018-10-18cputlb: serialize tlb updates with env->tlb_lockEmilio G. Cota
2018-10-18cputlb: fix assert_cpu_is_self macroEmilio G. Cota
2018-10-18exec: introduce tlb_initEmilio G. Cota
2018-10-18tcg: access cpu->icount_decr.u16.high with atomicsEmilio G. Cota
2018-10-18tcg: Implement CPU_LOG_TB_NOCHAIN during expansionRichard Henderson
2018-10-02accel/tcg: Remove dead codeThomas Huth
2018-10-02translator: fix breakpoint processingPavel Dovgalyuk
2018-09-26qht: drop ht argument from qht iteratorsEmilio G. Cota
2018-08-23KVM: cleanup unnecessary #ifdef KVM_CAP_...Paolo Bonzini
2018-08-17kvm: Use inhibit to prevent ballooning without synchronous mmuAlex Williamson
2018-08-14accel/tcg: Check whether TLB entry is RAM consistently with how we set it upPeter Maydell
2018-08-14accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code()Peter Maydell
2018-08-14accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAMPeter Maydell
2018-08-14accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint()Peter Maydell
2018-08-14accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookupsPeter Maydell
2018-08-14accel/tcg: Pass read access type through to io_readx()Peter Maydell
2018-07-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2018-07-16accel/tcg: Assert that tlb fill gave us a valid TLB entryPeter Maydell
2018-07-16accel/tcg: Use correct test when looking in victim TLB for codePeter Maydell
2018-07-16accel: Fix typo and grammar in commentStefan Weil
2018-07-09translate-all: honour CF_NOCACHE in tb_gen_codeEmilio G. Cota
2018-07-02Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2018-07-02accel/tcg: Avoid caching overwritten tlb entriesRichard Henderson
2018-07-02accel/tcg: Don't treat invalid TLB entries as needing recheckPeter Maydell
2018-07-02accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code()Peter Maydell
2018-07-02tcg: Define and use new tlb_hit() and tlb_hit_page() functionsPeter Maydell
2018-07-02translate-all: fix locking of TBs whose two pages share the same physical pageEmilio G. Cota
2018-07-02tcg: simplify !CONFIG_TCG handling of tb_invalidate_*Paolo Bonzini
2018-07-02tcg: Fix --disable-tcg build breakagePhilippe Mathieu-Daudé
2018-06-29Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2018-06-29i386/cpu: make -cpu host support monitor/mwaitMichael S. Tsirkin
2018-06-28kvm: Delete the slot if and only if the KVM_MEM_READONLY flag is changedShannon Zhao
2018-06-28move public invalidate APIs out of translate-all.{c,h}, clean upPaolo Bonzini
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-23 19:02:09 +0000