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2021-03-15hw/char: add goldfish-ttyLaurent Vivier
Implement the goldfish tty device as defined in https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT and based on the kernel driver code: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/goldfish.c Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210312214145.2936082-2-laurent@vivier.eu>
2021-03-15Merge remote-tracking branch 'remotes/philmd/tags/avr-20210315' into stagingPeter Maydell
AVR patches queue - Only reset 'interrupt_request' mask once all interrupts executed - Documentation and typo fixes # gpg: Signature made Sun 14 Mar 2021 23:45:34 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/avr-20210315: target/avr: Fix interrupt execution target/avr: Fix some comment spelling errors hw/avr/arduino: List board schematic links hw/misc/led: Add yellow LED Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-15Merge remote-tracking branch ↵Peter Maydell
'remotes/bkoppelmann2/tags/pull-tricore-20210314' into staging - Added triboard with tc27x_soc - Cleaned up get_physical_address() - Fixed corner case bugs in OPC2_32_RRPW_IMASK and OPC2_32_RRPW_IMASK insns # gpg: Signature made Sun 14 Mar 2021 13:53:11 GMT # gpg: using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14 # gpg: issuer "kbastian@mail.uni-paderborn.de" # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full] # Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14 * remotes/bkoppelmann2/tags/pull-tricore-20210314: target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2 tricore: fixed faulty conditions for extr and imask target/tricore: Remove unused definitions target/tricore: Pass MMUAccessType to get_physical_address() target/tricore: Replace magic value by MMU_DATA_LOAD definition tricore: added triboard with tc27x_soc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-15target/avr: Fix interrupt executionIvanov Arkasha
Only one interrupt is in progress at the moment. It is only necessary to set to reset interrupt_request after all interrupts have been executed. Signed-off-by: Ivanov Arkasha <ivanovrkasha@gmail.com> Message-Id: <20210312164754.18437-1-arkaisp2021@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
2021-03-15target/avr: Fix some comment spelling errorsLichang Zhao
I found that there are many spelling errors in the comments of qemu/target/avr. I used spellcheck to check the spelling errors and found some errors in the folder. Signed-off-by: Lichang Zhao <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Reviewed-by: Philippe Mathieu-Daude<f4bug@amsat.org> Message-Id: <20201009064449.2336-12-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
2021-03-15hw/avr/arduino: List board schematic linksPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Rolnik <mrolnik@gmail.com> Message-Id: <20210313165445.2113938-3-f4bug@amsat.org>
2021-03-15hw/misc/led: Add yellow LEDPhilippe Mathieu-Daudé
Add the yellow "lime" LED. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Rolnik <mrolnik@gmail.com> Message-Id: <20210313165445.2113938-2-f4bug@amsat.org>
2021-03-14Merge remote-tracking branch 'remotes/philmd/tags/mips-20210313' into stagingPeter Maydell
MIPS patches queue - Tidy up the GT64120 north bridge - Move XBurst Media eXtension Unit code to mxu_translate.c - Convert TX79 to decodetree # gpg: Signature made Sat 13 Mar 2021 22:44:44 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20210313: (27 commits) target/mips/tx79: Salvage instructions description comment target/mips: Remove 'C790 Multimedia Instructions' dead code target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree target/mips/tx79: Move PCPYH opcode to decodetree target/mips/translate: Simplify PCPYH using deposit_i64() target/mips/translate: Make gen_rdhwr() public target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree target/mips: Use gen_load_gpr[_hi]() when possible target/mips: Extract MXU code to new mxu_translate.c file target/mips: Introduce mxu_translate_init() helper target/mips: Simplify decode_opc_mxu() ifdef'ry target/mips: Convert decode_ase_mxu() to decodetree prototype target/mips: Rename decode_opc_mxu() as decode_ase_mxu() target/mips: Move MUL opcode check from decode_mxu() to decode_legacy() target/mips: Use OPC_MUL instead of OPC__MXU_MUL target/mips: Pass instruction opcode to decode_opc_mxu() target/mips: Remove unused CPUMIPSState* from MXU functions target/mips: Remove XBurst Media eXtension Unit dead code target/mips: Rewrite complex ifdef'ry ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-14Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/linux-user-for-6.0-pull-request' into staging linux-user pull request 20210313 - fix elfload - fix executable page of /proc/self/maps - add preserve-arg[0] support for binfmt_misc # gpg: Signature made Sat 13 Mar 2021 09:47:23 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-6.0-pull-request: linux-user/elfload: fix address calculation in fallback scenario linux-user/elfload: do not assume MAP_FIXED_NOREPLACE kernel support linux-user/elfload: munmap proper address in pgd_find_hole_fallback linux-user: manage binfmt-misc preserve-arg[0] flag linux-user: Fix executable page of /proc/self/maps Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-14Merge remote-tracking branch ↵Peter Maydell
'remotes/thuth-gitlab/tags/pull-request-2021-03-12' into staging * Move unit and bench tests into separate directories * Clean-up and improve gitlab-ci jobs * Drop the non-working "check-speed" makefile target * Minor documentation updates # gpg: Signature made Fri 12 Mar 2021 17:18:45 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2021-03-12: README: Add Documentation blurb MAINTAINERS: Merge the Gitlab-CI section into the generic CI section tests: remove "make check-speed" in favor of "make bench" gitlab-ci.yml: Merge check-crypto-old jobs into the build-crypto-old jobs gitlab-ci.yml: Merge one of the coroutine jobs with the tcg-disabled job gitlab-ci.yml: Add some missing dependencies to the jobs gitlab-ci.yml: Move build-tools-and-docs-debian to a better place tests: Move benchmarks into a separate folder tests: Move unit tests into a separate directory Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-14target/tricore: Fix OPC2_32_RRPW_EXTR for width=0Bastian Koppelmann
if width was 0 we would run into the assertion: qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o The instruction manual specifies undefined behaviour for this case. So we bring this in line with the golden Infineon simlator 'tsim', which simply writes 0 to the result in case of width=0. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2021-03-14target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2Bastian Koppelmann
if r3+1 and r2 are the same then we would overwrite r2 with our first move and use the wrong result for the shift. Thus we store the result from the mov in a temp. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2021-03-14tricore: fixed faulty conditions for extr and imaskAndreas Konopik
According to the TC 1.3.1. Architecture Manual [1; page 174], results are undefined, if pos + width > 32 and not 31 or if width = 0. We found this error because of a different behavior between qemu-tricore and the real tricore processor. For pos + width = 32, qemu-tricore did not generate any intermediate code and ran into a different state compared to the real hardware. [1] https://www.infineon.com/dgdl/tc_v131_instructionset_v138.pdf?fileId=db3a304412b407950112b409b6dd0352 [BK: Add the why to the commit message] Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de> Signed-off-by: David Brenken <david.brenken@efs-auto.de> Message-Id: <20210211115329.8984-2-david.brenken@efs-auto.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2021-03-14target/tricore: Remove unused definitionsPhilippe Mathieu-Daudé
Remove these confusing and unused definitions. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210127224255.3505711-4-f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2021-03-14target/tricore: Pass MMUAccessType to get_physical_address()Philippe Mathieu-Daudé
'int access_type' and ACCESS_INT are unused, drop them. Provide the mmu_idx argument to match other targets. 'int rw' is actually the MMUAccessType, rename it. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210127224255.3505711-3-f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2021-03-14target/tricore: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé
cpu_get_phys_page_debug() uses 'DATA LOAD' MMU access type. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210127224255.3505711-2-f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2021-03-14tricore: added triboard with tc27x_socAndreas Konopik
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de> Signed-off-by: David Brenken <david.brenken@efs-auto.de> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de> Message-Id: <20201109165055.10508-2-david.brenken@efs-auto.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2021-03-14Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20210314' into staging target-arm queue: * versal: Support XRAMs and XRAM controller * smmu: Various minor bug fixes * SVE emulation: fix bugs handling odd vector lengths * allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value * tests/acceptance: fix orangepi-pc acceptance tests * hw/timer/sse-timer: Propagate eventual error in sse_timer_realize() * hw/arm/virt: KVM: The IPA lower bound is 32 * npcm7xx: support MFT module * pl110, pxa2xx_lcd: tidy up template headers # gpg: Signature made Sun 14 Mar 2021 13:17:43 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210314: (39 commits) hw/display/pxa2xx: Inline template header hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header hw/display/pxa2xx: Apply brace-related coding style fixes to template header hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h hw/display/pxa2xx_lcd: Remove dest_width state field hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces hw/display/pl110: Remove use of BITS from pl110_template.h hw/display/pl110: Pull included-once parts of template header into pl110.c hw/display/pl110: Remove dead code for non-32-bpp surfaces tests/qtest: Test PWM fan RPM using MFT in PWM test hw/arm: Connect PWM fans in NPCM7XX boards hw/arm: Add MFT device to NPCM7xx Soc hw/misc: Add NPCM7XX MFT Module hw/misc: Add GPIOs for duty in NPCM7xx PWM hw/arm/virt: KVM: The IPA lower bound is 32 accel: kvm: Fix kvm_type invocation hw/timer/sse-timer: Propagate eventual error in sse_timer_realize() tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests tests/acceptance: update sunxi kernel from armbian to 5.10.16 tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-14hw/display/pxa2xx: Inline template headerPeter Maydell
The template header is now included only once; just inline its contents in hw/display/pxa2xx_lcd.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210211141515.8755-10-peter.maydell@linaro.org
2021-03-14hw/display/pxa2xx: Apply whitespace-only coding style fixes to template headerPeter Maydell
We're about to move code from the template header into pxa2xx_lcd.c. Before doing that, make coding style fixes so checkpatch doesn't complain about the patch which moves the code. This commit is whitespace changes only: * avoid hard-coded tabs * fix ident on function prototypes * no newline before open brace on array definitions Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210211141515.8755-9-peter.maydell@linaro.org
2021-03-14hw/display/pxa2xx: Apply brace-related coding style fixes to template headerPeter Maydell
We're about to move code from the template header into pxa2xx_lcd.c. Before doing that, make coding style fixes so checkpatch doesn't complain about the patch which moves the code. This commit fixes missing braces in the SKIP_PIXEL() macro definition and in if() statements. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210211141515.8755-8-peter.maydell@linaro.org
2021-03-14hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.hPeter Maydell
Now that BITS is always 32, expand out all its uses in the template header, including removing now-useless uses of the glue() macro. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210211141515.8755-7-peter.maydell@linaro.org
2021-03-14hw/display/pxa2xx_lcd: Remove dest_width state fieldPeter Maydell
Since the dest_width is now always 4 because the output surface is 32bpp, we can replace the dest_width state field with a constant. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210211141515.8755-6-peter.maydell@linaro.org
2021-03-14hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfacesPeter Maydell
For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel. Remove the legacy dead code from the pxa2xx_lcd display device which was handling the possibility that the console surface was some other format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210211141515.8755-5-peter.maydell@linaro.org
2021-03-14hw/display/pl110: Remove use of BITS from pl110_template.hPeter Maydell
BITS is always 32, so remove all uses of it from the template header, by dropping the trailing '32' from the draw function names and not constructing the name of rgb_to_pixel32() via the glue() macro. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210211141515.8755-4-peter.maydell@linaro.org
2021-03-14hw/display/pl110: Pull included-once parts of template header into pl110.cPeter Maydell
The pl110_template.h header has a doubly-nested multiple-include pattern: * pl110.c includes it once for each host bit depth (now always 32) * every time it is included, it includes itself 6 times, to account for multiple guest device pixel and byte orders Now we only have to deal with 32-bit host bit depths, we can move the code corresponding to the outer layer of this double-nesting to be directly in pl110.c and reduce the template header to a single layer of nesting. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210211141515.8755-3-peter.maydell@linaro.org
2021-03-14hw/display/pl110: Remove dead code for non-32-bpp surfacesPeter Maydell
For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel. Remove the legacy dead code from the pl110 display device which was handling the possibility that the console surface was some other format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210211141515.8755-2-peter.maydell@linaro.org
2021-03-13target/mips/tx79: Salvage instructions description commentPhilippe Mathieu-Daudé
This comment describing the tx79 opcodes is helpful. As we will implement these instructions in tx79_translate.c, move the comment there. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-15-f4bug@amsat.org>
2021-03-13target/mips: Remove 'C790 Multimedia Instructions' dead codePhilippe Mathieu-Daudé
We have almost 400 lines of code full of /* TODO */ comments which end calling gen_reserved_instruction(). As we are not going to implement them, and all the caller's switch() default cases already call gen_reserved_instruction(), we can remove this altogether. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-14-f4bug@amsat.org>
2021-03-13target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetreePhilippe Mathieu-Daudé
Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD (Parallel Copy Upper Doubleword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-13-f4bug@amsat.org>
2021-03-13target/mips/tx79: Move PCPYH opcode to decodetreePhilippe Mathieu-Daudé
Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-12-f4bug@amsat.org>
2021-03-13target/mips/translate: Simplify PCPYH using deposit_i64()Philippe Mathieu-Daudé
Simplify the PCPYH (Parallel Copy Halfword) instruction by using multiple calls to deposit_i64() which can be optimized by some TCG backends. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-11-f4bug@amsat.org>
2021-03-13target/mips/translate: Make gen_rdhwr() publicPhilippe Mathieu-Daudé
We will use gen_rdhwr() outside of translate.c, make it public. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-28-f4bug@amsat.org>
2021-03-13target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetreePhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-10-f4bug@amsat.org>
2021-03-13target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetreePhilippe Mathieu-Daudé
Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
2021-03-13target/mips: Use gen_load_gpr[_hi]() when possiblePhilippe Mathieu-Daudé
Use gen_load_gpr[_hi]() instead of open coding it. Patch generated using the following spatch script: @gen_load_gpr@ identifier reg_idx; expression tcg_reg; @@ -if (reg_idx == 0) { - tcg_gen_movi_tl(tcg_reg, 0); -} else { - tcg_gen_mov_tl(tcg_reg, cpu_gpr[reg_idx]); -} +gen_load_gpr(tcg_reg, reg_idx); @gen_load_gpr_hi@ identifier reg_idx; expression tcg_reg; @@ -if (reg_idx == 0) { - tcg_gen_movi_i64(tcg_reg, 0); -} else { - tcg_gen_mov_i64(tcg_reg, cpu_gpr_hi[reg_idx]); -} +gen_load_gpr_hi(tcg_reg, reg_idx); Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210308131604.460693-1-f4bug@amsat.org>
2021-03-13target/mips: Extract MXU code to new mxu_translate.c filePhilippe Mathieu-Daudé
Extract 1600+ lines from the big translate.c into a new file. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-14-f4bug@amsat.org>
2021-03-13target/mips: Introduce mxu_translate_init() helperPhilippe Mathieu-Daudé
Extract the MXU register initialization code from mips_tcg_init() as a new mxu_translate_init() helper. Make it public and replace !TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS == 32' check to elide this code at preprocessing time. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-13-f4bug@amsat.org>
2021-03-13target/mips: Simplify decode_opc_mxu() ifdef'ryPhilippe Mathieu-Daudé
By making the prototype public and checking 'TARGET_LONG_BITS == 32' we let the compiler elide the decode_opc_mxu() call. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-12-f4bug@amsat.org>
2021-03-13target/mips: Convert decode_ase_mxu() to decodetree prototypePhilippe Mathieu-Daudé
To easily convert MXU code to decodetree, making it return a boolean. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-11-f4bug@amsat.org>
2021-03-13target/mips: Rename decode_opc_mxu() as decode_ase_mxu()Philippe Mathieu-Daudé
Use "decode_{isa,ase,ext}_$name()" function name pattern for public decodetree entrypoints. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-10-f4bug@amsat.org>
2021-03-13target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()Philippe Mathieu-Daudé
Move the check for MUL opcode from decode_opc_mxu() callee to decode_opc_legacy() caller, so we can simplify the ifdef'ry and elide the call in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-9-f4bug@amsat.org>
2021-03-13target/mips: Use OPC_MUL instead of OPC__MXU_MULPhilippe Mathieu-Daudé
We already have a macro and definition to extract / check the Special2 MUL opcode. Use it instead of the unnecessary OPC__MXU_MUL macro. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-8-f4bug@amsat.org>
2021-03-13target/mips: Pass instruction opcode to decode_opc_mxu()Philippe Mathieu-Daudé
In the next commit we'll make decode_opc_mxu() match decodetree prototype by returning a boolean. First pass ctx->opcode as an argument. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-7-f4bug@amsat.org>
2021-03-13target/mips: Remove unused CPUMIPSState* from MXU functionsPhilippe Mathieu-Daudé
None of these MXU functions use their CPUMIPSState* env argument, remove it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-6-f4bug@amsat.org>
2021-03-13target/mips: Remove XBurst Media eXtension Unit dead codePhilippe Mathieu-Daudé
All these unimplemented MXU opcodes end up calling gen_reserved_instruction() which is the default switch case in decode_opc_mxu(). The translate.c file is already big enough and hard to maintain, remove 1300 lines of unnecessary code and /* TODO */ comments. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-5-f4bug@amsat.org>
2021-03-13target/mips: Rewrite complex ifdef'ryPhilippe Mathieu-Daudé
No need for this obfuscated ifdef'ry, KISS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-4-f4bug@amsat.org>
2021-03-13target/mips/meson: Restrict mips-semi.c to TCGPhilippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-3-f4bug@amsat.org>
2021-03-13target/mips/meson: Introduce mips_tcg source setPhilippe Mathieu-Daudé
Introduce the 'mips_tcg' source set to collect TCG specific files. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-2-f4bug@amsat.org>
2021-03-13hw/mips/gt64xxx: Trace accesses to ISD registersPhilippe Mathieu-Daudé
Trace all accesses to Internal Space Decode (ISD) registers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20210309142630.728014-6-f4bug@amsat.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-27 14:04:28 +0000