aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng
2021-09-21target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang
2021-09-21docs/system/riscv: sifive_u: Update U-Boot instructionsBin Meng
2021-09-21hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transferFrank Chang
2021-09-21hw/dma: sifive_pdma: allow non-multiple transaction size transactionsGreen Wan
2021-09-21hw/dma: sifive_pdma: claim bit must be set before DMA transactionsFrank Chang
2021-09-21hw/dma: sifive_pdma: reset Next* registers when Control.claim is setFrank Chang
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis
2021-09-21hw/timer: Add SiFive PWM supportAlistair Francis
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: sifive_clint: Use RISC-V CPU GPIO linesAlistair Francis
2021-09-21target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis
2021-09-21target/riscv: Fix satp writeLIU Zhiwei
2021-09-21target/riscv: Update the ePMP CSR addressAlistair Francis
2021-09-20Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into st...Peter Maydell
2021-09-20Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' ...Peter Maydell
2021-09-20hvf: Add Apple Silicon supportAlexander Graf
2021-09-20hvf: Introduce hvf_arch_init() callbackAlexander Graf
2021-09-20hvf: Add execute to dirty log permission bitmapAlexander Graf
2021-09-20arm: Move PMC register definitions to internals.hAlexander Graf
2021-09-20hw/intc: Set GIC maintenance interrupt level to only 0 or 1Shashi Mallela
2021-09-20target/arm: Consolidate ifdef blocks in resetPeter Maydell
2021-09-20target/arm: Always clear exclusive monitor on resetPeter Maydell
2021-09-20target/arm: Don't skip M-profile reset entirely in user modePeter Maydell
2021-09-20elf2dmp: Fail cleanly if PDB file specifies zero block_sizePeter Maydell
2021-09-20elf2dmp: Check curl_easy_setopt() return valuePeter Maydell
2021-09-20hw/arm/aspeed: Add Fuji machine typePeter Delevoryas
2021-09-20hw/arm/aspeed: Allow machine to set UART defaultPeter Delevoryas
2021-09-20hw/arm/aspeed: Initialize AST2600 UART clock selection registersPeter Delevoryas
2021-09-20arm/aspeed: Add DPS310 to Witherspoon and RainierJoel Stanley
2021-09-20hw/misc: Add Infineon DPS310 sensor modelJoel Stanley
2021-09-20aspeed: Emulate the AST2600A3Joel Stanley
2021-09-20arm/aspeed: rainier: Add i2c eeproms and muxesJoel Stanley
2021-09-20misc/pca9552: Fix LED status register indexing in pca955x_get_led()Andrew Jeffery
2021-09-20hw: aspeed_gpio: Clarify GPIO controller nameJoel Stanley
2021-09-20hw: aspeed_gpio: Simplify 1.8V definesJoel Stanley
2021-09-20watchdog: aspeed: Fix sequential control writesAndrew Jeffery
2021-09-20watchdog: aspeed: Sanitize control register valuesAndrew Jeffery
2021-09-20hw: arm: aspeed: Enable mac0/1 instead of mac1/2 for g220aGuenter Roeck
2021-09-20hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evbGuenter Roeck
2021-09-19Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-2021...Peter Maydell
2021-09-17virtio-net: fix use after unmap/free for sgJason Wang
2021-09-17ebpf: only include in system emulatorsPaolo Bonzini
2021-09-16Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.2-pull-re...Peter Maydell