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2019-03-20prep: do not select I82374Paolo Bonzini
It is only needed through I82378, which also selects it. Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-20hw/i386/Kconfig: PC uses I8257, not I82374Paolo Bonzini
CONFIG_I82374 is not needed for PC machines, since they create i8257 directly instead. Reported-by: Miroslav Rezanina <mrezanin@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-18hw/char/parallel: Make it possible to compile also without CONFIG_PARALLELThomas Huth
For the downstream distribution of QEMU, we want to compile without CONFIG_PARALLEL. Commit 9157eee1b1c076ff3 already moved the function parallel_hds_isa_init() (which is still required for linking) into a file that is included anyway, but commit bb3d5ea858e7f888563a moved it to a separate file which is only compiled again if CONFIG_PARALLEL is set. To be able to link QEMU again without CONFIG_PARALLEL, the file should be considered for linking for all targets that have CONFIG_ISA_BUS. And while we're at it, add a proper comment in there with the rationale for the separate file. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1552297854-25847-1-git-send-email-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-18target/i386: sev: Do not pin the ram device memory regionSingh, Brijesh
The RAM device presents a memory region that should be handled as an IO region and should not be pinned. In the case of the vfio-pci, RAM device represents a MMIO BAR and the memory region is not backed by pages hence KVM_MEMORY_ENCRYPT_REG_REGION fails to lock the memory range. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1667249 Cc: Alex Williamson <alex.williamson@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20190204222322.26766-3-brijesh.singh@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-18memory: Fix the memory region type assignment orderSingh, Brijesh
Currently, a callback registered through the RAMBlock notifier is not able to get the memory region type (i.e callback is not able to use memory_region_is_ram_device function). This is because mr->ram assignment happens _after_ the memory is allocated whereas the callback is executed during allocation. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1667249 Suggested-by: Alex Williamson <alex.williamson@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20190204222322.26766-2-brijesh.singh@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-18kconfig: add dependencies on CONFIG_MSI_NONBROKENPaolo Bonzini
For devices that require msi_init/msix_init to succeed, add a dependency on CONFIG_MSI_NONBROKEN. This will prevent those devices from appearing in a binary that cannot instantiate them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-18kconfig: add CONFIG_MSI_NONBROKENPaolo Bonzini
Not all interrupt controllers have a working implementation of message-signalled interrupts; in some cases, the guest may expect MSI to work but it won't due to the buggy or lacking emulation. In QEMU this is represented by the "msi_nonbroken" variable. This patch adds a new configuration symbol enabled whenever the binary contains an interrupt controller that will set "msi_nonbroken". We can then use it to remove devices that cannot be possibly added to the machine, because they require MSI. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-18riscv: plic: Set msi_nonbroken as trueAlistair Francis
Set msi_nonbroken as true for the PLIC. According to the comment located here: https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38 the msi_nonbroken variable should be set to true even if they don't support MSI. In this case that is what we are doing as we don't support MSI. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reported-by: Andrea Bolognani <abologna@redhat.com> Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com> Message-Id: <256afbb2da005dc62c159b0f4a4fc0d95c050660.1552679970.git.alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-14Merge remote-tracking branch 'remotes/stsquad/tags/pull-gitdm-next-120319-1' ↵Peter Maydell
into staging Final gitdm updates for 4.0 # gpg: Signature made Tue 12 Mar 2019 19:33:51 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-gitdm-next-120319-1: contrib: gitdm: add a mapping for Janus Technologies contrib: gitdm: another IBM email contrib: gitdm: add more individual contributors contrib: gitdm: Update Wave Computing group contrib: gitdm: Update domain-map Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-14Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-for-4.0-120319-1' into staging Final testing fixes for 4.0 - various CI tweaks and fixes - fixes for some tcg tests - addition of system tcg tests # gpg: Signature made Tue 12 Mar 2019 17:07:24 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-for-4.0-120319-1: (26 commits) .travis.yml: add softmmu check-tcg tests .travis.yml: separate softfloat from check-tcg tests/tcg/arm: account for pauth randomness tests/tcg/i386: add memory test to exercise softmmu tests/tcg/i386: add system mode Hello World test tests/tcg: provide a minilib for system tests tests/tcg: enable cris base user-mode tests tests/tcg/cris: align mul operations tests/tcg/cris: comment out the ccs test tests/tcg: split cris tests into bare and libc directories tests/tcg/cris: cleanup sys.c tests/docker: add fedora-cris-cross compilers tests/tcg/arm: add ARMv6-M UNDEFINED 32-bit instruction test tests/tcg/xtensa: enable system tests tests/docker: add debian-xtensa-cross image tests/tcg/mips: fix hello-mips compilation tests/tcg: add gdb runner variant tests/tcg: split run-test into user and system variants tests/tcg: add QEMU_OPT option for test runner tests/tcg: enable tcg tests for softmmu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-14Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* ASAN fixes # gpg: Signature made Tue 12 Mar 2019 14:35:59 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: test-migration: fix memory leak migration: fix memory leak test-bdrv-graph-mod: fix Error leak test-char: fix undefined behavior Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-14Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Pull request * Add 'drop-cache=on|off' option to file-posix.c. The default is on. Disabling the option fixes a QEMU 3.0.0 performance regression when live migrating on the same host with cache.direct=off. # gpg: Signature made Wed 13 Mar 2019 11:07:48 GMT # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: file-posix: add drop-cache=on|off option Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-14Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into ↵Peter Maydell
staging Slirp updates Daniel P. Berrangé (1): configure: remove slirp submodule support that doesn't exist yet Marc-André Lureau (1): slirp: remove empty state.h # gpg: Signature made Wed 13 Mar 2019 21:18:35 GMT # gpg: using RSA key E61DBB15D4172BDEC97E92D9DB550E89F0FA54F3 # gpg: Good signature from "Samuel Thibault <samuel.thibault@aquilenet.fr>" [unknown] # gpg: aka "Samuel Thibault <sthibault@debian.org>" [marginal] # gpg: aka "Samuel Thibault <samuel.thibault@gnu.org>" [unknown] # gpg: aka "Samuel Thibault <samuel.thibault@inria.fr>" [marginal] # gpg: aka "Samuel Thibault <samuel.thibault@labri.fr>" [marginal] # gpg: aka "Samuel Thibault <samuel.thibault@ens-lyon.org>" [marginal] # gpg: aka "Samuel Thibault <samuel.thibault@u-bordeaux.fr>" [unknown] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 900C B024 B679 31D4 0F82 304B D017 8C76 7D06 9EE6 # Subkey fingerprint: E61D BB15 D417 2BDE C97E 92D9 DB55 0E89 F0FA 54F3 * remotes/thibault/tags/samuel-thibault: configure: remove slirp submodule support that doesn't exist yet slirp: remove empty state.h Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-13Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' ↵Peter Maydell
into staging target/riscv: Convert to decodetree Bastian: this patchset converts the RISC-V decoder to decodetree in four major steps: 1) Convert 32-bit instructions to decodetree [Patch 1-15]: Many of the gen_* functions are called by the decode functions for 16-bit and 32-bit functions. If we move translation code from the gen_* functions to the generated trans_* functions of decode-tree, we get a lot of duplication. Therefore, we mostly generate calls to the old gen_* function which are properly replaced after step 2). Each of the trans_ functions are grouped into files corresponding to their ISA extension, e.g. addi which is in RV32I is translated in the file 'trans_rvi.inc.c'. 2) Convert 16-bit instructions to decodetree [Patch 16-18]: All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus, we convert the arguments in the 16 bit trans_ function to the arguments of the corresponding 32 bit instruction and call the 32 bit trans_ function. 3) Remove old manual decoding in gen_* function [Patch 19-29]: this move all manual translation code into the trans_* instructions of decode tree, such that we can remove the old decode_* functions. Palmer: This, with some additional cleanup patches, passed Alistar's testing on rv32 and rv64 as well as my testing on rv64, so I think it's good to go. I've run my standard test against this exact tag. I still don't have a Mac to try this on, sorry! # gpg: Signature made Wed 13 Mar 2019 13:44:49 GMT # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.0-sf4: (29 commits) target/riscv: Remove decode_RV32_64G() target/riscv: Remove gen_system() target/riscv: Rename trans_arith to gen_arith target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Remove shift and slt insn manual decoding target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: Remove manual decoding from gen_store() target/riscv: Remove manual decoding from gen_load() target/riscv: Remove manual decoding from gen_branch() target/riscv: Remove gen_jalr() target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert RV priv insns to decodetree target/riscv: Convert RV64D insns to decodetree target/riscv: Convert RV32D insns to decodetree target/riscv: Convert RV64F insns to decodetree target/riscv: Convert RV32F insns to decodetree target/riscv: Convert RV64A insns to decodetree ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-13configure: remove slirp submodule support that doesn't exist yetDaniel P. Berrangé
The slirp code is not yet split off into a separate repository, so configuring QEMU to use slirp as a submodule is premature. This causes the non-existant "slirp" to be requested from git when syncing submodules. This in turn appears to be cause of non-deterministic failures some developers are seeing with QEMU's submodule sync process. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20190313173157.30504-1-berrange@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2019-03-13slirp: remove empty state.hMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20190313173949.2369-1-marcandre.lureau@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2019-03-13Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190313-pull-request' ↵Peter Maydell
into staging ui: better unicode support for curses, v2. # gpg: Signature made Wed 13 Mar 2019 07:29:44 GMT # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20190313-pull-request: curses: add option to specify VGA font encoding iconv: detect and make curses depend on it Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-13Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
pci, pc, virtio: features, fixes, cleanups intel-iommu scalable option pcie acs emulation beginning for vhost-user-blk reconnect and of vhost-user backend work misc fixes and cleanups Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 13 Mar 2019 02:52:02 GMT # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (26 commits) i386, acpi: check acpi_memory_hotplug capacity in pre_plug gen_pcie_root_port: Add ACS (Access Control Services) capability pcie: Add a simple PCIe ACS (Access Control Services) helper function vhost-user-blk: Add support to get/set inflight buffer libvhost-user: Support tracking inflight I/O in shared memory libvhost-user: Introduce vu_queue_map_desc() libvhost-user: Remove unnecessary FD flag check for event file descriptors vhost-user: Support transferring inflight buffer between qemu and backend nvdimm: use NVDIMM_ACPI_IO_LEN for the proper IO size nvdimm: use *function* directly instead of allocating it again nvdimm: fix typo in nvdimm_build_nvdimm_devices argument intel_iommu: add scalable-mode option to make scalable mode work intel_iommu: add 256 bits qi_desc support intel_iommu: scalable mode emulation libvhost-user: add vu_queue_unpop() libvhost-user-glib: export vug_source_new() vhost-user: split vhost_user_read() vhost-user: wrap some read/write with retry handling libvhost-user: exit by default on VHOST_USER_NONE vhost-user: simplify vhost_user_init/vhost_user_cleanup ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-13Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' into ↵Peter Maydell
staging Pull request # gpg: Signature made Tue 12 Mar 2019 20:23:08 GMT # gpg: using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full] # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jnsnow/tags/bitmaps-pull-request: (22 commits) tests/qemu-iotests: add bitmap resize test 246 block/qcow2-bitmap: Allow resizes with persistent bitmaps block/qcow2-bitmap: Don't check size for IN_USE bitmap docs/interop/qcow2: Improve bitmap flag in_use specification bitmaps: Fix typo in function name block/dirty-bitmaps: implement inconsistent bit block/dirty-bitmaps: disallow busy bitmaps as merge source block/dirty-bitmaps: prohibit removing readonly bitmaps block/dirty-bitmaps: prohibit readonly bitmaps for backups block/dirty-bitmaps: add block_dirty_bitmap_check function block/dirty-bitmap: add inconsistent status block/dirty-bitmaps: add inconsistent bit iotests: add busy/recording bit test to 124 blockdev: remove unused paio parameter documentation block/dirty-bitmaps: move comment block block/dirty-bitmaps: unify qmp_locked and user_locked calls block/dirty-bitmap: explicitly lock bitmaps with successors nbd: change error checking order for bitmaps block/dirty-bitmap: change semantics of enabled predicate block/dirty-bitmap: remove set/reset assertions against enabled bit ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # tests/qemu-iotests/group
2019-03-13Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Block layer patches: - file-posix: Make auto-read-only dynamic - Add x-blockdev-reopen QMP command - Finalize block-latency-histogram QMP command - gluster: Build fixes for newer lib version # gpg: Signature made Tue 12 Mar 2019 19:30:31 GMT # gpg: using RSA key 7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (28 commits) qemu-iotests: Test the x-blockdev-reopen QMP command block: Add an 'x-blockdev-reopen' QMP command block: Remove the AioContext parameter from bdrv_reopen_multiple() block: Add bdrv_reset_options_allowed() block: Add a 'mutable_opts' field to BlockDriver block: Allow changing the backing file on reopen block: Allow omitting the 'backing' option in certain cases block: Handle child references in bdrv_reopen_queue() block: Add 'keep_old_opts' parameter to bdrv_reopen_queue() block: Freeze the backing chain for the duration of the stream job block: Freeze the backing chain for the duration of the mirror job block: Freeze the backing chain for the duration of the commit job block: Allow freezing BdrvChild links nvme: fix write zeroes offset and count file-posix: Make auto-read-only dynamic file-posix: Prepare permission code for fd switching file-posix: Lock new fd in raw_reopen_prepare() file-posix: Store BDRVRawState.reopen_state during reopen file-posix: Factor out raw_reconfigure_getfd() file-posix: Fix bdrv_open_flags() for snapshot=on ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-13Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20190312' into stagingPeter Maydell
Break out documentation to docs/devel/. Add support for pattern groups. Other misc cleanups for multiple decode functions. # gpg: Signature made Tue 12 Mar 2019 16:59:37 GMT # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-dt-20190312: decodetree: Properly diagnose fields overflowing an insn decodetree: Prefix extract function names with decode_function decodetree: Allow +- to begin a number initializing a field decodetree: Produce clean output for an empty input file decodetree: Add --static-decode option test/decode: Add tests for PatternGroups decodetree: Allow grouping of overlapping patterns decodetree: Do not unconditionaly return from Pattern.output_code decodetree: Ensure build_tree does not include values outside insnmask decodetree: Document the usefulness of argument sets decodetree: Move documentation to docs/devel/decodetree.rst MAINTAINERS: Add scripts/decodetree.py to the TCG section Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-13file-posix: add drop-cache=on|off optionStefan Hajnoczi
Commit dd577a26ff03b6829721b1ffbbf9e7c411b72378 ("block/file-posix: implement bdrv_co_invalidate_cache() on Linux") introduced page cache invalidation so that cache.direct=off live migration is safe on Linux. The invalidation takes a significant amount of time when the file is large and present in the page cache. Normally this is not the case for cross-host live migration but it can happen when migrating between QEMU processes on the same host. On same-host migration we don't need to invalidate pages for correctness anyway, so an option to skip page cache invalidation is useful. I investigated optimizing invalidation and detecting same-host migration, but both are hard to achieve so a user-visible option will suffice. As a bonus this option means that the cache invalidation feature will now be detectable by libvirt via QMP schema introspection. Suggested-by: Neil Skrypuch <neil@tembosocial.com> Tested-by: Neil Skrypuch <neil@tembosocial.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190307164941.3322-1-stefanha@redhat.com Message-Id: <20190307164941.3322-1-stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2019-03-13target/riscv: Remove decode_RV32_64G()Bastian Koppelmann
decodetree handles all instructions now so the fallback is not necessary anymore. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove gen_system()Bastian Koppelmann
with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann
manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann
gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann
We now utilizes argument-sets of decodetree such that no manual decoding is necessary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann
trans_jalr() is the only caller, so move the code into trans_jalr(). Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann
we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann
this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>