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2016-06-24target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSAAleksandar Markovic
Function msa_reset() is updated so that flag snan_bit_is_one is properly set to 0. By applying this patch, a number of incorrect MSA behaviors that require IEEE 754-2008 compliance will be fixed. Those are behaviors that (up to the moment of applying this patch) did not get the desired functionality from SoftFloat library with respect to distinguishing between quiet and signaling NaN, getting default NaN values (both quiet and signaling), establishing if a floating point number is NaN or not, etc. Two examples: * FMAX, FMIN will now correctly detect and propagate NaNs. * FCLASS.D ans FCLASS.S will now correcty detect NaN flavors. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24linux-user: Update preprocessor constants for Mips-specific e_flags bitsAleksandar Markovic
Missing values EF_MIPS_FP64 and EF_MIPS_NAN2008 added. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd()Aleksandar Markovic
Only for Mips platform, and only for cases when snan_bit_is_one is 0, correct the order of argument comparisons in pickNaNMulAdd(). For more info, see [1], page 53, section "3.5.3 NaN Propagation". [1] "MIPS Architecture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module", Imagination Technologies LTD, Revision 1.12, February 3, 2016 Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [leon.alrae@imgtec.com: * reworded the subject of the patch * swapped if/else code blocks to match the commit description] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24softfloat: For Mips only, correct default NaN valuesAleksandar Markovic
Only for Mips platform, and only for cases when snan_bit_is_one is 0, correct default NaN values (in their 16-, 32-, and 64-bit flavors). For more info, see [1], page 84, Table 6.3 "Value Supplied When a New Quiet NaN Is Created", and [2], page 52, Table 3.7 "Default NaN Encodings". [1] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies LTD, Revision 6.04, November 13, 2015 [2] "MIPS Architecture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module", Imagination Technologies LTD, Revision 1.12, February 3, 2016 Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24softfloat: Clean code format in fpu/softfloat-specialize.hAleksandar Markovic
fpu/softfloat-specialize.h is the most critical file in SoftFloat library, since it handles numerous differences between platforms in relation to floating point arithmetics. This patch makes the code in this file more consistent format-wise, and hopefully easier to debug and maintain. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic
This patch modifies SoftFloat library so that it can be configured in run-time in relation to the meaning of signaling NaN bit, while, at the same time, strictly preserving its behavior on all existing platforms. Background: In floating-point calculations, there is a need for denoting undefined or unrepresentable values. This is achieved by defining certain floating-point numerical values to be NaNs (which stands for "not a number"). For additional reasons, virtually all modern floating-point unit implementations use two kinds of NaNs: quiet and signaling. The binary representations of these two kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally, the first bit of mantissa). Up to 2008, standards for floating-point did not specify all details about binary representation of NaNs. More specifically, the meaning of the bit that is used for distinguishing between signaling and quiet NaNs was not strictly prescribed. (IEEE 754-2008 was the first floating-point standard that defined that meaning clearly, see [1], p. 35) As a result, different platforms took different approaches, and that presented considerable challenge for multi-platform emulators like QEMU. Mips platform represents the most complex case among QEMU-supported platforms regarding signaling NaN bit. Up to the Release 6 of Mips architecture, "1" in signaling NaN bit denoted signaling NaN, which is opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of that, Mips architecture for SIMD (also known as MSA, or vector instructions) also specifies signaling bit in accordance to IEEE standard. MSA unit can be implemented with both pre-Release 6 and Release 6 main processor units. QEMU uses SoftFloat library to implement various floating-point-related instructions on all platforms. The current QEMU implementation allows for defining meaning of signaling NaN bit during build time, and is implemented via preprocessor macro called SNAN_BIT_IS_ONE. On the other hand, the change in this patch enables SoftFloat library to be configured in run-time. This configuration is meant to occur during CPU initialization, at the moment when it is definitely known what desired behavior for particular CPU (or any additional FPUs) is. The change is implemented so that it is consistent with existing implementation of similar cases. This means that structure float_status is used for passing the information about desired signaling NaN bit on each invocation of SoftFloat functions. The additional field in float_status is called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE. IMPORTANT: This change is not meant to create any change in emulator behavior or functionality on any platform. It just provides the means for SoftFloat library to be used in a more flexible way - in other words, it will just prepare SoftFloat library for usage related to Mips platform and its specifics regarding signaling bit meaning, which is done in some of subsequent patches from this series. Further break down of changes: 1) Added field snan_bit_is_one to the structure float_status, and correspondent setter function set_snan_bit_is_one(). 2) Constants <float16|float32|float64|floatx80|float128>_default_nan (used both internally and externally) converted to functions <float16|float32|float64|floatx80|float128>_default_nan(float_status*). This is necessary since they are dependent on signaling bit meaning. At the same time, for the sake of code cleanup and simplicity, constants <floatx80|float128>_default_nan_<low|high> (used only internally within SoftFloat library) are removed, as not needed. 3) Added a float_status* argument to SoftFloat library functions XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_), XXX_maybe_silence_nan(XXX a_). This argument must be present in order to enable correct invocation of new version of functions XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128> here) 4) Updated code for all platforms to reflect changes in SoftFloat library. This change is twofolds: it includes modifications of SoftFloat library functions invocations, and an addition of invocation of function set_snan_bit_is_one() during CPU initialization, with arguments that are appropriate for each particular platform. It was established that all platforms zero their main CPU data structures, so snan_bit_is_one(0) in appropriate places is not added, as it is not needed. [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer Society, August 29, 2008. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [leon.alrae@imgtec.com: * cherry-picked 2 chunks from patch #2 to fix compilation warnings] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-23Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160623' ↵Peter Maydell
into staging ppc patch queue for 2016-06-23 Currently outstanding patches for spapr, target-ppc and related devices. This batch has: * Significant new progress towards full support for hypervisor mode * Assorted bugfixes * Some preliminary patches towards dynamic DMA window support The last involves a change to memory.c, which Paolo has said I can take through this tree. # gpg: Signature made Thu 23 Jun 2016 06:47:53 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.7-20160623: ppc: Disable huge page support if it is not available for main RAM ppc: Add P7/P8 Power Management instructions ppc: Move exception generation code out of line ppc: Turn a bunch of booleans from int to bool ppc: Add real mode CI load/store instructions for P7 and P8 ppc: Rework generation of priv and inval interrupts ppc: Fix generation if ISI/DSI vs. HV mode ppc: Fix POWER7 and POWER8 exception definitions ppc: fix exception model for HV mode ppc: define a default LPCR value ppc: Fix rfi/rfid/hrfi/... emulation memory: Add reporting of supported page sizes ppc: Improve emulation of THRM registers target-ppc: Fix rlwimi, rlwinm, rlwnm again ppc64: disable gen_pause() for linux-user mode tests: Use '+=' to add additional tests, not '=' powerpc/mm: Update the WIMG check during H_ENTER Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-23Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20160622-2' into ↵Peter Maydell
staging usb: add hotplug support for usb-bot and usb-uas. # gpg: Signature made Wed 22 Jun 2016 12:45:46 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/pull-usb-20160622-2: usb-uas: hotplug support usb-bot: hotplug support usb: Add QOM property "attached". usb: make USBDevice->attached bool usb-storage: qcow2 encryption support is finally gone, zap dead code Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-23Merge remote-tracking branch 'remotes/sstabellini/tags/xen-20160622-tag' ↵Peter Maydell
into staging xen-20160622 # gpg: Signature made Wed 22 Jun 2016 12:45:56 BST # gpg: using RSA key 0x894F8F4870E1AE90 # gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" # Primary key fingerprint: D04E 33AB A51F 67BA 07D3 0AEA 894F 8F48 70E1 AE90 * remotes/sstabellini/tags/xen-20160622-tag: xen: move xen_sysdev to xen_backend.c xen: fix qdisk BLKIF_OP_DISCARD for 32/64 word size mix xen: fix style of hw/block/xen_blkif.h Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-23ppc: Disable huge page support if it is not available for main RAMThomas Huth
On powerpc, we must only signal huge page support to the guest if all memory areas are capable of supporting huge pages. The commit 2d103aae8765 ("fix hugepage support when using memory-backend-file") already fixed the case when the user specified the mem-path property for NUMA memory nodes instead of using the global "-mem-path" option. However, there is one more case where it currently can go wrong. When specifying additional memory DIMMs without using NUMA, e.g. qemu-system-ppc64 -enable-kvm ... -m 1G,slots=2,maxmem=2G \ -device pc-dimm,id=dimm-mem1,memdev=mem1 -object \ memory-backend-file,policy=default,mem-path=/...,size=1G,id=mem1 the code in getrampagesize() currently assumes that huge pages are possible since they are enabled for the mem1 object. But since the main RAM is not backed by a huge page filesystem, the guest Linux kernel then crashes very quickly after being started. So in case the we've got "normal" memory without NUMA and without the global "-mem-path" option, we must not announce huge pages to the guest. Since this is likely a mis-configuration by the user, also spill out a message in this case. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt
This adds the ISA 2.06 and later power management instructions (doze, nap, sleep and rvwinkle) and associated wakeup cause testing in LPCR Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Move exception generation code out of lineBenjamin Herrenschmidt
There's no point inlining this, if you hit the exception case you exit anyway, and not inlining saves about 100K of code size (and cache footprint). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: removed '__attribute__((noinline))' from original patch ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Turn a bunch of booleans from int to boolBenjamin Herrenschmidt
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Add real mode CI load/store instructions for P7 and P8Benjamin Herrenschmidt
Those instructions are only available in hypervisor real mode and allow cache inhibited garded access to devices in that mode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Rework generation of priv and inval interruptsBenjamin Herrenschmidt
Recent server processors use the Hypervisor Emulation Assistance interrupt for illegal instructions and *some* type of SPR accesses. Also the code was always generating inval instructions even for priv violations due to setting the wrong flags Finally, the checking for PR/HV was open coded everywhere. This reworks it all, using little helper macros for checking, and adding the HV interrupt (which gets converted back to program check in the slow path of excp_helper.c on CPUs that don't want it). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Fix generation if ISI/DSI vs. HV modeBenjamin Herrenschmidt
Under some circumstances, we need to direct ISI and DSI interrupts at the hypervisor, turning them into HISI/HDSI, and using different SPRs (HDSISR and HDAR) depending on the combination of MSR_DR and the corresponding VPM bits in LPCR. This moves part of the code into helpers that are fixed to select the right exception type and registers. On pre-P7 processors, LPCR is 0 which provides the old behaviour of directing the interrupts at the supervisor. Thanks to Andrei Warkentin for finding a bug when HV=1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: Merged a fix on POWERPC_EXCP_HDSI fixing the condition on msr_hv, from Andrei Warkentin <andrey.warkentin@gmail.com> ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Fix POWER7 and POWER8 exception definitionsBenjamin Herrenschmidt
We were initializing unused ones and missing some Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: fix exception model for HV modeBenjamin Herrenschmidt
This properly implements LPES0 handling for HV vs. !HV mode and removes the unsupported LPES1. This has been removed from the specs since ISA v2.07. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: AIL implementation was fixed in commit 5c94b2a5e5ef. This patch only contains the bits of the original patch related to LPES0 handling, adapted commit log. fixed checkpatch.pl errors. ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: define a default LPCR valueBenjamin Herrenschmidt
This allows us to set the appropriate LPCR bits which will be used when fixing the exception model for the HV mode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: previous commit 26a7f1291bb5 did not include the LPCR setting as it was not needed at the time, adapted commit log ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Fix rfi/rfid/hrfi/... emulationBenjamin Herrenschmidt
This reworks emulation of the various "rfi" variants. I removed some masking bits that I couldn't make sense of, the only bit that I am aware we should mask here is POW, the CPU's MSR mask should take care of the rest. This also fixes some problems when running 32-bit userspace under a 64-bit kernel. This patch broke 32bit OpenBIOS when run under a 970 cpu. A fix was proposed here : https://www.coreboot.org/pipermail/openbios/2016-June/009452.html Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: updated the commit log with the reference of the openbios fix ] Signed-off-by: Cédric Le Goater <clg@kaod.org> [dwg: Remove hunk which disabled rfi on 64-bit CPUS. The change was correct, but we need to fix OpenBIOS before applying it] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22usb-uas: hotplug supportGerd Hoffmann
Make attached property settable and turns off auto-attach in case the device was hotplugged. Hotplugging works simliar to usb-bot now. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 1465984019-28963-6-git-send-email-kraxel@redhat.com
2016-06-22usb-bot: hotplug supportGerd Hoffmann
This patch marks usb-bot as hot-pluggable device, makes attached property settable and turns off auto-attach in case the device was hotplugged. Hot-plugging a usb-bot device with one or more scsi devices can be done this way now: (1) device-add usb-bot,id=foo (2) device-add scsi-{hd,cd},bus=foo.0,lun=0 (2b) optionally add more devices (luns 0 ... 15). (3) qom-set foo.attached = true Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 1465984019-28963-5-git-send-email-kraxel@redhat.com
2016-06-22usb: Add QOM property "attached".Gerd Hoffmann
USB devices in attached state are visible to the guest. This patch adds a QOM property for this. Write access is opt-in per device. Some devices manage attached state automatically (usb-host, usb-serial, usb-redir), so we can't enable write access universally but have to do it on a case by case base. So far, no device opts in. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 1465984019-28963-4-git-send-email-kraxel@redhat.com [ minor codestyle fix ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-06-22usb: make USBDevice->attached boolGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 1465984019-28963-3-git-send-email-kraxel@redhat.com
2016-06-22usb-storage: qcow2 encryption support is finally gone, zap dead codeGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 1465984019-28963-2-git-send-email-kraxel@redhat.com
2016-06-22xen: move xen_sysdev to xen_backend.cJuergen Gross
Commit 9432e53a5bc88681b2d3aec4dac9db07c5476d1b added xen_sysdev as a system device to serve as an anchor for removable virtual buses. This introduced a build failure for non-x86 builds with CONFIG_XEN_BACKEND set, as xen_sysdev was defined in a x86 specific file while being consumed in an architecture independent source. Move the xen_sysdev definition and initialization to xen_backend.c to avoid the build failure. Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2016-06-22xen: fix qdisk BLKIF_OP_DISCARD for 32/64 word size mixJuergen Gross
In case the word size of the domU and qemu running the qdisk backend differ BLKIF_OP_DISCARD will not work reliably, as the request structure in the ring have different layouts for different word size. Correct this by copying the request structure in case of different word size element by element in the BLKIF_OP_DISCARD case, too. Signed-off-by: Juergen Gross <jgross@suse.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2016-06-22xen: fix style of hw/block/xen_blkif.hJuergen Gross
Fix hw/block/xen_blkif.h to match qemu coding style. Signed-off-by: Juergen Gross <jgross@suse.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2016-06-22memory: Add reporting of supported page sizesAlexey Kardashevskiy
Every IOMMU has some granularity which MemoryRegionIOMMUOps::translate uses when translating, however this information is not available outside the translate context for various checks. This adds a get_min_page_size callback to MemoryRegionIOMMUOps and a wrapper for it so IOMMU users (such as VFIO) can know the minimum actual page size supported by an IOMMU. As IOMMU MR represents a guest IOMMU, this uses TARGET_PAGE_SIZE as fallback. This removes vfio_container_granularity() and uses new helper in memory_region_iommu_replay() when replaying IOMMU mappings on added IOMMU memory region. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Alex Williamson <alex.williamson@redhat.com> [dwg: Removed an unnecessary calculation] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22ppc: Improve emulation of THRM registersBenjamin Herrenschmidt
The 75x and 74xx processors have some thermal monitoring SPRs that some OSes such as MacOS do use. Our current "dumb" implementation isn't good enough and will cause some versions of MacOS to hang during boot. This lifts an improved emulation from MacOnLinux and adapts it to qemu, thus fixing the problem. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fixed typo in comment, a number of minor checkpatch warnings, and a compile failure with CONFIG_USER_ONLY] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22target-ppc: Fix rlwimi, rlwinm, rlwnm againRichard Henderson
In 63ae0915f8ec, I arranged to use a 32-bit rotate, without considering the effect of a mask value that wraps around to the high bits of the word. [dwg: In 2e11b15 this was partially fixed, but an edge case was still incorrect, which this fixes] Signed-off-by: Richard Henderson <rth@twiddle.net> [dwg: Folded with a revert of 2e11b15, an earlier buggy version of this patch which already went upstream] Tested-by: Anton Blanchard <anton@samba.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22ppc64: disable gen_pause() for linux-user modeLaurent Vivier
While trying to install a fedora container with "lxc-create -t fedora -- -I qemu-ppc64" the installation abort with the following error: qemu: fatal: Unknown exception 0x65537. Aborting NIP 0000004000927924 LR 00000040009e325c CTR 0000004000927480 XER 0000000000000000 CPU#0 MSR 9000000102806000 HID0 0000000000000000 HF 9000000002806000 iidx 3 didx 3 TB 00248932 1069155773327487 GPR00 00000040009e325c 00000040007ff800 0000004000aba098 0000000000000000 GPR04 00000040007ff878 0000004000dcb588 0000004000dcb830 0000004000a7a098 GPR08 0000000000000000 0000000000000000 00000040007ff878 0000004000927960 GPR12 0000000022022448 0000004000e2aef0 0000000000000000 0000000000000000 GPR16 0000000000000000 0000000000000000 0000000000000002 0000000000000001 GPR20 0000000000000000 0000000000000000 0000000000000000 0000004000800699 GPR24 0000004000e13320 0000000000000000 0000004000ac9ad8 0000004000ac9ae0 GPR28 0000000000000001 00000000100210a0 0000000000000000 0000000000000038 CR 22022442 [ E E - E E G G E ] RES ffffffffffffffff FPR00 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPSCR 0000000000000000 /usr/share/lxc/templates/lxc-fedora: line 487: 26661 Aborted (core dumped) chroot . yum -y --nogpgcheck --installroot /run/install install python rpm yum I've bisected until the commit: commit b68e60e6f0d2865e961a800fb8db96a7fc6494c4 Author: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: Tue May 3 18:03:33 2016 +0200 ppc: Get out of emulation on SMT "OR" ops Otherwise tight loops at smt_low for example, which OPAL does, eat so much CPU that we can't boot a kernel anymore. With that, I can boot 8 CPUs just fine with powernv. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> We can fix that by preventing to send EXCP_HLT in the case of linux-user mode, as the main loop doesn't know how to manage it. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22tests: Use '+=' to add additional tests, not '='Thomas Huth
The recent commit that added the prom-env-test accidentially overwrote the check-qtest-ppc-y, check-qtest-ppc64-y and check-qtest-sparc-y variables instead of extending them. Fixes: fcbf4a3c0c576eec1321f9cff4fa0dd8e0b1a82f Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22powerpc/mm: Update the WIMG check during H_ENTERAneesh Kumar K.V
Support for 0 value for memeory coherence is optional and with ppc64 we can always enable memory coherence. Linux kernel did that during the development of 4.7 kernel. But that resulted in failure in Qemu in H_ENTER hcall due to below check. The mentioned change was reverted in the kernel and kernel right now enable memory coherence only if cache inhibited is not set. Nevertheless update qemu WIMG flag check to cover the case where we enable memory coherence along with cache inhibited flag. In order to handle older and newer kernel version consider both Cache inhibitted and (cache inhibitted | memory conference) as valid values for wimg flags. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-21Merge remote-tracking branch 'remotes/stsquad/tags/pull-travis-20160621-1' ↵Peter Maydell
into staging This pull request contains: - disable sparse testing - add trusty build target - add libnfs-dev for NFS block driver These are the same patches posted last week for any last minute review. # gpg: Signature made Tue 21 Jun 2016 10:06:34 BST # gpg: using RSA key 0xFBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-travis-20160621-1: .travis.yml: disable Sparse testing .travis.yml: add trusty GCE target .travis.yml: add libnfs-dev for NFS block driver Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-21milkymist: fix tmu2.c build failure (missing error.h include)Gerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Michael Walle <michael@walle.cc> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-21Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into ↵Peter Maydell
staging qemu-sparc update # gpg: Signature made Mon 20 Jun 2016 21:55:23 BST # gpg: using RSA key 0x5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-signed: MAINTAINERS: remove Blue Swirl as SPARC maintainer MAINTAINERS: add Artyom Tarasenko as SPARC maintainer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-20Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell
into staging # gpg: Signature made Mon 20 Jun 2016 21:29:27 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/tracing-pull-request: (42 commits) trace: split out trace events for linux-user/ directory trace: split out trace events for qom/ directory trace: split out trace events for target-ppc/ directory trace: split out trace events for target-s390x/ directory trace: split out trace events for target-sparc/ directory trace: split out trace events for net/ directory trace: split out trace events for audio/ directory trace: split out trace events for ui/ directory trace: split out trace events for hw/alpha/ directory trace: split out trace events for hw/arm/ directory trace: split out trace events for hw/acpi/ directory trace: split out trace events for hw/vfio/ directory trace: split out trace events for hw/s390x/ directory trace: split out trace events for hw/pci/ directory trace: split out trace events for hw/ppc/ directory trace: split out trace events for hw/9pfs/ directory trace: split out trace events for hw/i386/ directory trace: split out trace events for hw/isa/ directory trace: split out trace events for hw/sd/ directory trace: split out trace events for hw/sparc/ directory ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-20MAINTAINERS: remove Blue Swirl as SPARC maintainerMark Cave-Ayland
Blue is no longer active in the QEMU project, so remove him from the list of SPARC maintainers. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> CC: Blue Swirl <blauwirbel@gmail.com>
2016-06-20MAINTAINERS: add Artyom Tarasenko as SPARC maintainerMark Cave-Ayland
Artyom has been working on QEMU's SPARC emulation for several years, providing initial support for Solaris under qemu-system-sparc and more recently bugfixes for qemu-system-sparc64 and TCG patch reviews. As work progresses on improving emulation for sun4u machines and beyond, Artyom has agreed to take on co-maintainership of SPARC with a focus on 64-bit architecture. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
2016-06-20Merge remote-tracking branch 'remotes/mwalle/tags/lm32-queue/20160620' into ↵Peter Maydell
staging lm32/milkymist: some qomifying # gpg: Signature made Mon 20 Jun 2016 17:27:53 BST # gpg: using RSA key 0xB458ABB0D8D378E3 # gpg: Good signature from "Michael Walle <michael@walle.cc>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2190 3E48 4537 A7C2 90CE 3EB2 B458 ABB0 D8D3 78E3 * remotes/mwalle/tags/lm32-queue/20160620: milkymist: update specification URLs hw/intc: QOM'ify lm32_pic.c hw/display: QOM'ify milkymist-vgafb.c hw/display: QOM'ify milkymist-tmu2.c hw/timer: QOM'ify milkymist_sysctl hw/timer: QOM'ify lm32_timer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-20trace: split out trace events for linux-user/ directoryDaniel P. Berrange
Move all trace-events for files in the linux-user/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-id: 1466066426-16657-41-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for qom/ directoryDaniel P. Berrange
Move all trace-events for files in the qom/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-40-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for target-ppc/ directoryDaniel P. Berrange
Move all trace-events for files in the target-ppc/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 1466066426-16657-39-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for target-s390x/ directoryDaniel P. Berrange
Move all trace-events for files in the target-s390x/ directory to their own file. [Added missing newline in target-s390x/trace-events as suggested by Cornelia Huck <cornelia.huck@de.ibm.com>. --Stefan] Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Message-id: 1466066426-16657-38-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for target-sparc/ directoryDaniel P. Berrange
Move all trace-events for files in the target-sparc/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-37-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for net/ directoryDaniel P. Berrange
Move all trace-events for files in the net/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-36-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for audio/ directoryDaniel P. Berrange
Move all trace-events for files in the audio/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-35-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for ui/ directoryDaniel P. Berrange
Move all trace-events for files in the ui/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-34-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for hw/alpha/ directoryDaniel P. Berrange
Move all trace-events for files in the hw/alpha/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-33-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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