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2014-01-01configure: Python tests must be done before help messageStefan Weil
The help message uses $python and displays its value, so that macro should be tested and set early. With this modification, configure --help displays the correct value (usually python -B) and no longer creates several *.pyc files. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-01-01configure: Rewrite code for help messageStefan Weil
In the new form most lines of the code now look like the final output: there is no leading echo command and the lines are shorter. The resulting output is nearly identical: the only difference is a blank character which was deliberately removed: @@ -8,7 +8,7 @@ --interp-prefix=PREFIX where to find shared libraries, etc. use %M for cpu name [/usr/gnemul/qemu-%M] --target-list=LIST set target list (default: build everything) - Available targets: alpha-softmmu arm-softmmu + Available targets: alpha-softmmu arm-softmmu cris-softmmu i386-softmmu lm32-softmmu m68k-softmmu microblaze-softmmu microblazeel-softmmu mips-softmmu mips64-softmmu mips64el-softmmu mipsel-softmmu Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23fix -boot strict regressed in commit 6ef4716Amos Kong
Commit 6ef4716 cleaned up parsing of -boot option argument, but accidentally dropped parameter strict. It should have been updated exactly like parameter menu. Do that. Signed-off-by: Amos Kong <akong@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23vl: make boot_strict variable static (not used outside vl.c)Michael Tokarev
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Amos Kong <akong@redhat.com>
2013-12-23x86: only allow real mode to access 32bit without LMAAlexander Graf
When we're running in non-64bit mode with qemu-system-x86_64 we can still end up with virtual addresses that are above the 32bit boundary if a segment offset is set up. GNU Hurd does exactly that. It sets the segment offset to 0x80000000 and puts its EIP value to 0x8xxxxxxx to access low memory. This doesn't hit us when we enable paging, as there we just mask away the unused bits. But with real mode, we assume that vaddr == paddr which is wrong in this case. Real hardware wraps the virtual address around at the 32bit boundary. So let's do the same. This fixes booting GNU Hurd in qemu-system-x86_64 for me. Reported-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23linux-user: Use macro TARGET_NSIG_WORDS where possibleStefan Weil
This improves readability and simplifies the code. Cc: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23exynos4210: Use macro ARRAY_SIZE where possibleStefan Weil
This improves readability and simplifies the code. Cc: Dmitry Solodkiy <d.solodkiy@samsung.com> Cc: Evgeny Voevodin <e.voevodin@samsung.com> Cc: Igor Mitsyanko <i.mitsyanko@gmail.com> Cc: Maksim Kozlov <m.kozlov@samsung.com> Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23ui/cocoa: Use macro ARRAY_SIZE where possibleStefan Weil
This improves readability and simplifies the code. Cc: Andreas Färber <andreas.faerber@web.de> Cc: Anthony Liguori <aliguori@amazon.com> Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23misc: Use macro ARRAY_SIZE where possibleStefan Weil
This improves readability and simplifies the code. Cc: Anthony Liguori <aliguori@amazon.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23openrisc: Fix spelling in comment (transaltion -> translation)Stefan Weil
I also removed two hyphens in the same comment. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Jia Liu <proljc@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23hw/arm/highbank: Simplify code (memory region in device state)Stefan Weil
The memory region can be included by value instead of by reference in the device state. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-22PPC: Fix compilation with TCG debugAlexander Graf
The recent VSX patches broken compilation of QEMU when configurated with --enable-debug, as it was treating "target long" TCG variables as "i64" which is not true for 32bit targets. This patch fixes all the places that the compiler has found to use the correct variable type and if necessary manually cast. Reported-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-12-21Merge tag 'signed-s390-for-upstream' of git://github.com/agraf/qemuAurelien Jarno
Patch queue for s390 - 2013-12-18 This covers mostly minor bug fixes and implements the SIGP START hypercall which allows to start a remote CPU without changing its state. Cornelia Huck (1): s390x/kvm: Fix diagnose handling. Thomas Huth (7): s390x/kvm: Removed duplicated SIGP defines s390x/kvm: Removed s390_store_status stub s390x/kvm: Fix coding style in handle_sigp() s390x/kvm: Implemented SIGP START s390x/kvm: Simplified the calculation of the SIGP order code s390x/kvm: Fixed condition code for unknown SIGP orders s390x/ioinst: CHSC has to set a condition code * tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu: s390x/ioinst: CHSC has to set a condition code s390x/kvm: Fixed condition code for unknown SIGP orders s390x/kvm: Simplified the calculation of the SIGP order code s390x/kvm: Implemented SIGP START s390x/kvm: Fix coding style in handle_sigp() s390x/kvm: Removed s390_store_status stub s390x/kvm: Removed duplicated SIGP defines s390x/kvm: Fix diagnose handling.
2013-12-21target-sh4: Use new qemu_ld/st opcodesAurelien Jarno
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-12-21target-mips: Use new qemu_ld/st opcodesAurelien Jarno
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-12-21tcg/i386: fix a commentAurelien Jarno
The comments apply to 8-bit stores, not 8-byte stores. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-12-19Merge remote-tracking branch 'agraf/tags/signed-ppc-for-upstream' into stagingAnthony Liguori
Patch queue for ppc - 2013-12-20 Alexander Graf (3): PPC: Use default pci bus name for grackle and heathrow roms: Flush icache when writing roms to guest memory PPC: Add VSX to hflags Alexey Kardashevskiy (5): powerpc: add PVR mask support target-ppc: move POWER7+ to a separate family spapr-rtas: replace return code constants with macros spapr-rtas: add ibm, (get|set)-system-parameter spapr: make sure RMA is in first mode of first memory node Greg Kurz (1): target-ppc: add stubs for KVM breakpoints Paolo Bonzini (1): spapr: tie spapr-nvram to -pflash Paul Mackerras (1): spapr: limit numa memory regions by ram size Peter Crosthwaite (2): device_tree: s/qemu_devtree/qemu_fdt globally device_tree: qemu_fdt_setprop: Rename val_array arg Tom Musta (19): Declare and Enable VSX Add MSR VSX and Associated Exception Add VSX Instruction Decoders Add VSR to Global Registers Add lxvd2x Add stxvd2x Add xxpermdi Add lxsdx Add lxvdsx Add lxvw4x Add stxsdx Add stxvw4x Add VSX Scalar Move Instructions Add VSX Vector Move Instructions Add Power7 VSX Logical Instructions Add xxmrgh/xxmrgl Add xxsel Add xxspltw Add xxsldwi * agraf/tags/signed-ppc-for-upstream: (32 commits) spapr: limit numa memory regions by ram size spapr: make sure RMA is in first mode of first memory node device_tree: qemu_fdt_setprop: Rename val_array arg device_tree: s/qemu_devtree/qemu_fdt globally PPC: Add VSX to hflags Add xxsldwi Add xxspltw Add xxsel Add xxmrgh/xxmrgl Add Power7 VSX Logical Instructions Add VSX Vector Move Instructions Add VSX Scalar Move Instructions roms: Flush icache when writing roms to guest memory spapr: tie spapr-nvram to -pflash PPC: Use default pci bus name for grackle and heathrow spapr-rtas: add ibm, (get|set)-system-parameter spapr-rtas: replace return code constants with macros target-ppc: move POWER7+ to a separate family Add stxvw4x Add stxsdx ...
2013-12-20spapr: limit numa memory regions by ram sizePaul Mackerras
This makes sure that all NUMA memory blocks reside within RAM or have zero length. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr: make sure RMA is in first mode of first memory nodeAlexey Kardashevskiy
The SPAPR specification says that the RMA starts at the LPAR's logical address 0 and is the first logical memory block reported in the LPAR’s device tree. So SLOF only maps the first block and that block needs to span the full RMA. This makes sure that the RMA area is where SLOF expects it. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20device_tree: qemu_fdt_setprop: Rename val_array argPeter Crosthwaite
Looking at the implementation, this doesn't really have a lot to do with arrays. Its just a pointer to a buffer and is passed through to the wrapped fn (qemu_fdt_setprop) unchanged. So rename to make it consistent with libfdt, which in the wrapped function just calls it "val". Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20device_tree: s/qemu_devtree/qemu_fdt globallyPeter Crosthwaite
The qemu_devtree API is a wrapper around the fdt_ set of APIs. Rename accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [agraf: also convert hw/arm/virt.c] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20PPC: Add VSX to hflagsAlexander Graf
We generate different code depending on whether MSR_VSX is set or clear, so it needs to be part of our hflags too which indicate whether we're still in the same translation block cache bucket. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxsldwiTom Musta
This patch adds the VSX Shift Left Double by Word Immediate (xxsldwi) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxspltwTom Musta
This patch adds the VSX Splat Word (xxsplatw) instruction. This is the first instruction to use the UIM immediate field and consequently a decoder is also added. V2: reworked implementation per Richard Henderson's comments. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxselTom Musta
This patch adds the VSX Select (xxsel) instruction. The xxsel instruction has four VSR operands. Thus the xC instruction decoder is added. The xxsel instruction is massively overloaded in the opcode table since only bits 26 and 27 are opcode bits. This overloading is done in matrix fashion with two macros (GEN_XXSEL_ROW and GEN_XX_SEL). V2: (1) eliminated unecessary XXSEL macro (2) tighter implementation using tcg_gen_andc_i64. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxmrgh/xxmrglTom Musta
This patch adds the VSX Merge High Word and VSX Merge Low Word instructions. V2: Now implemented using deposit (per Richard Henderson's comment) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add Power7 VSX Logical InstructionsTom Musta
This patch adds the VSX logical instructions that are defined by the Version 2.06 Power ISA (aka Power7): - xxland - xxlandc - xxlor - xxlxor - xxlnor Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSX Vector Move InstructionsTom Musta
This patch adds the vector move instructions: - xvabsdp - Vector Absolute Value Double-Precision - xvnabsdp - Vector Negative Absolute Value Double-Precision - xvnegdp - Vector Negate Double-Precision - xvcpsgndp - Vector Copy Sign Double-Precision - xvabssp - Vector Absolute Value Single-Precision - xvnabssp - Vector Negative Absolute Value Single-Precision - xvnegsp - Vector Negate Single-Precision - xvcpsgnsp - Vector Copy Sign Single-Precision V3: Per Paolo Bonzini's suggestion, used a temporary for the sign mask and andc. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSX Scalar Move InstructionsTom Musta
This patch adds the VSX scalar move instructions: - xsabsdp (Scalar Absolute Value Double-Precision) - xsnabspd (Scalar Negative Absolute Value Double-Precision) - xsnegdp (Scalar Negate Double-Precision) - xscpsgndp (Scalar Copy Sign Double-Precision) A common generator macro (VSX_SCALAR_MOVE) is added since these instructions vary only slightly from each other. Macros to support VSX XX2 and XX3 form opcodes are also added. These macros handle the overloading of "opcode 2" space (instruction bits 26:30) caused by AX and BX bits (29 and 30, respectively). V3: Per feedback from Paolo Bonzini, moved the sign mask into a temporary and used andc. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20roms: Flush icache when writing roms to guest memoryAlexander Graf
We use the rom infrastructure to write firmware and/or initial kernel blobs into guest address space. So we're basically emulating the cache off phase on very early system bootup. That phase is usually responsible for clearing the instruction cache for anything it writes into cachable memory, to ensure that after reboot we don't happen to execute stale bits from the instruction cache. So we need to invalidate the icache every time we write a rom into guest address space. We do not need to do this for every DMA since the guest expects it has to flush the icache manually in that case. This fixes random reboot issues on e5500 (booke ppc) for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr: tie spapr-nvram to -pflashPaolo Bonzini
spapr-nvram's drive property is currently connected to a non-existent "-machine nvram=<drivename>" option. Instead, tie it to -pflash like other non-volatile RAM devices. This provides the following possibilities for adding a backend for the sPAPR non-volatile RAM: * -pflash filename * -drive if=pflash,file=filename,format=raw,... * -drive if=none,file=filename,format=raw,id=foo,... -global spapr-nvram.drive=foo Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20PPC: Use default pci bus name for grackle and heathrowAlexander Graf
There's no good reason to call our bus "pci" rather than let the default bus name take over ("pci.0"). The big downside to calling it different from anyone else is that tools that pass -device get confused. They are looking for a bus "pci.0" rather than "pci". To make life easier for everyone, let's just drop the name override. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr-rtas: add ibm, (get|set)-system-parameterAlexey Kardashevskiy
This adds very basic handlers for ibm,get-system-parameter and ibm,set-system-parameter RTAS calls. The only parameter handled at the moment is "platform-processor-diagnostics-run-mode" which is always disabled and does not support changing. This is expected to make "ppc64_cpu --run-mode=1" happy. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: s/papameter/parameter/g] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr-rtas: replace return code constants with macrosAlexey Kardashevskiy
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20target-ppc: move POWER7+ to a separate familyAlexey Kardashevskiy
So far POWER7+ was a part of POWER7 family. However it has a different PVR base value so in order to support PVR masks, it needs a separate family class. This adds a new family class, PVR base and mask values and moves Power7+ v2.1 CPU to a new family. The class init function is copied from the POWER7 family. This defines a firmware name for the new family as "PowerPC,POWER7+" instead of previously used "PowerPC,POWER7" from the POWER7 family. The reason for that is that the Sapphire firmware (a h0st firmware) uses "PowerPC,POWER7+" already and since no specification defines exactly the CPU nodes naming in the device tree, we better stay in sync with the host firmware. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxvw4xTom Musta
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxsdxTom Musta
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvw4xTom Musta
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x) instruction. V2: changed to use deposit_i64 per Richard Henderson's review. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvdsxTom Musta
This patch adds the Load VSX Vector Doubleword & Splat Indexed (lxvdsx) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxsdxTom Musta
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx) instruction. The lower 8 bytes of the target register are undefined; this implementation leaves those bytes unaltered. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxpermdiTom Musta
This patch adds the xxpermdi instruction. The instruction uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX and BX). This results in overloading of the opcode table with aliases, which can be seen in the GEN_XX3FORM_DM macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxvd2xTom Musta
This patch adds the stxvd2x instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvd2xTom Musta
This patch adds the lxvd2x instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSR to Global RegistersTom Musta
This patch adds VSX VSRs to the the list of global register indices. More specifically, it adds the lower halves of the first 32 VSRs to the list of global register indices. The upper halves of the first 32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs are already defined via the cpu_avrh[] and cpu_avrl[] arrays. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSX Instruction DecodersTom Musta
This patch adds decoders for the VSX fields XT, XS, XA, XB and DM. The first four are split fields and a general helper for these types of fields is also added. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add MSR VSX and Associated ExceptionTom Musta
This patch adds support for the VSX bit of the PowerPC Machine State Register (MSR) as well as the corresponding VSX Unavailable exception. The VSX bit is added to the defined bits masks of the Power7 and Power8 CPU models. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Declare and Enable VSXTom Musta
This patch adds the flag POWERPC_FLAG_VSX to the list of defined flags and also adds this flag to the list of supported features of the Power7 and Power8 CPUs. Additionally, the VSX instructions are added to the list of TCG-enabled instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20powerpc: add PVR mask supportAlexey Kardashevskiy
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and a CPU version in lower 16 bits. Since there is no significant change in behavior between versions, there is no point to add every single CPU version in QEMU's CPU list. Also, new CPU versions of already supported CPU won't break the existing code. This adds PVR value/mask support for KVM, i.e. for -cpu host option. As CPU family class name for POWER7 is "POWER7-family", there is no need to touch aliases. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20target-ppc: add stubs for KVM breakpointsGreg Kurz
The latest update to v3.13-rc3 (bf63839f) breaks the ppc build with KVM: kvm-all.o: In function `kvm_update_guest_debug': kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug' kvm-all.o: In function `kvm_insert_breakpoint': kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint' kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint' kvm-all.o: In function `kvm_remove_breakpoint': kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint' kvm-all.o: In function `kvm_remove_all_breakpoints': kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints' We need stubs until something gets implemented. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-19Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131217' into ↵Anthony Liguori
staging target-arm queue: * AES instruction support for 32 bit ARM * pflash01: much better emulation of 2x16bit and similar configs where multiple flash devices are banked together * fixed CBAR handling on Zynq, Highbank * initial AArch64 KVM control support * first two chunks of patches for A64 instruction emulation * new board: canon-a1100 (Canon DIGIC SoC) * new board: cubieboard (Allwinner A10 SoC) # gpg: Signature made Tue 17 Dec 2013 12:18:39 PM PST using RSA key ID 14360CDE # gpg: Can't check signature: public key not found # By Alexander Graf (14) and others # Via Peter Maydell * pmaydell/tags/pull-target-arm-20131217: (62 commits) MAINTAINERS: add myself to maintain allwinner-a10 hw/arm: add cubieboard support hw/arm: add allwinner a10 SoC support hw/intc: add allwinner A10 interrupt controller hw/timer: add allwinner a10 timer vmstate: Add support for an array of ptimer_state * MAINTAINERS: Document 'Canon DIGIC' machine hw/arm/digic: add NOR ROM support hw/arm/digic: add UART support hw/arm/digic: add timer support hw/arm/digic: prepare DIGIC-based boards support hw/arm: add very initial support for Canon DIGIC SoC target-arm: A64: add support for logical (immediate) insns target-arm: A64: add support for 1-src CLS insn host-utils: add clrsb32/64 - count leading redundant sign bits target-arm: A64: add support for bitfield insns target-arm: A64: add support for 1-src REV insns target-arm: A64: add support for 1-src RBIT insn target-arm: A64: add support for 1-src data processing and CLZ target-arm: A64: add support for 2-src shift reg insns ... Message-id: 1387312160-12318-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@amazon.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-13 22:03:33 +0000